Volume 3 General-Purpose and System Instructions (794097), страница 47
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The pseudo-descriptor is a memory location containing the GDTR base and limit. In legacyand compatibility mode, the pseudo-descriptor is 6 bytes; in 64-bit mode, it is 10 bytes.If the operand size is 16 bits, the high-order byte of the 6-byte pseudo-descriptor is not used.
The lowertwo bytes specify the 16-bit limit and the third, fourth, and fifth bytes specify the 24-bit base address.The high-order byte of the GDTR is filled with zeros.If the operand size is 32 bits, the lower two bytes specify the 16-bit limit and the upper four bytesspecify a 32-bit base address.In 64-bit mode, the lower two bytes specify the 16-bit limit and the upper eight bytes specify a 64-bitbase address. In 64-bit mode, operand-size prefixes are ignored and the operand size is forced to 64bits; therefore, the pseudo-descriptor is always 10 bytes.This instruction is only used in operating system software and must be executed at CPL 0. It istypically executed once in real mode to initialize the processor before switching to protected mode.LGDT is a serializing instruction.MnemonicOpcodeDescriptionLGDT mem16:320F 01 /2Loads mem16:32 into the global descriptor table register.LGDT mem16:640F 01 /2Loads mem16:64 into the global descriptor table register.Related InstructionsLIDT, LLDT, LTR, SGDT, SIDT, SLDT, STRrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode, #UDXStack, #SSXInstruction ReferenceXCause of ExceptionXThe operand was a register.XA memory address exceeded the stack segment limit or wasnon-canonical.LGDT273AMD64 TechnologyException24594—Rev.
3.13—July 2007VirtualReal 8086 ProtectedXGeneral protection,#GPPage fault, #PF274XCause of ExceptionXA memory address exceeded the data segment limit or wasnon-canonical.XCPL was not 0.XThe new GDT base address was non-canonical.XA null data segment was used to reference memory.XA page fault resulted from the execution of the instruction.LGDTInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyLIDTLoad Interrupt Descriptor Table RegisterLoads the pseudo-descriptor specified by the source operand into the interrupt descriptor table register(IDTR). The pseudo-descriptor is a memory location containing the IDTR base and limit. In legacyand compatibility mode, the pseudo-descriptor is six bytes; in 64-bit mode, it is 10 bytes.If the operand size is 16 bits, the high-order byte of the 6-byte pseudo-descriptor is not used. The lowertwo bytes specify the 16-bit limit and the third, fourth, and fifth bytes specify the 24-bit base address.The high-order byte of the IDTR is filled with zeros.If the operand size is 32 bits, the lower two bytes specify the 16-bit limit and the upper four bytesspecify a 32-bit base address.In 64-bit mode, the lower two bytes specify the 16-bit limit, and the upper eight bytes specify a 64-bitbase address.
In 64-bit mode, operand-size prefixes are ignored and the operand size is forced to 64bits; therefore, the pseudo-descriptor is always 10 bytes.This instruction is only used in operating system software and must be executed at CPL 0. It isnormally executed once in real mode to initialize the processor before switching to protected mode.LIDT is a serializing instruction.MnemonicOpcodeDescriptionLIDT mem16:320F 01 /3Loads mem16:32 into the interrupt descriptor table register.LIDT mem16:640F 01 /3Loads mem16:64 into the interrupt descriptor table register.Related InstructionsLGDT, LLDT, LTR, SGDT, SIDT, SLDT, STRrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode, #UDXStack, #SSXInstruction ReferenceXCause of ExceptionXThe operand was a register.XA memory address exceeded the stack segment limit or wasnon-canonical.LIDT275AMD64 TechnologyException24594—Rev.
3.13—July 2007VirtualReal 8086 ProtectedXGeneral protection,#GPPage fault, #PF276XCause of ExceptionXA memory address exceeded the data segment limit or wasnon-canonical.XCPL was not 0.XThe new IDT base address was non-canonical.XA null data segment was used to reference memory.XA page fault resulted from the execution of the instruction.LIDTInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyLLDTLoad Local Descriptor Table RegisterLoads the specified segment selector into the visible portion of the local descriptor table (LDT). Theprocessor uses the selector to locate the descriptor for the LDT in the global descriptor table.
It thenloads this descriptor into the hidden portion of the LDTR.If the source operand is a null selector, the LDTR is marked invalid and all references to descriptors inthe LDT will generate a general protection exception (#GP), except for the LAR, VERR, VERW orLSL instructions.In legacy and compatibility modes, the LDT descriptor is 8 bytes long and contains a 32-bit baseaddress.In 64-bit mode, the LDT descriptor is 16-bytes long and contains a 64-bit base address. The LDTdescriptor type (02h) is redefined in 64-bit mode for use as the 16-byte LDT descriptor.This instruction must be executed in protected mode. It is only provided for use by operating systemsoftware at CPL 0.LLDT is a serializing instruction.MnemonicOpcodeLLDTreg/mem16DescriptionLoad the 16-bit segment selector into the local descriptortable register and load the LDT descriptor from the GDT.0F 00 /2Related InstructionsLGDT, LIDT, LTR, SGDT, SIDT, SLDT, STRrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode, #UDXXCause of ExceptionThis instruction is only recognized in protected mode.Segment not present,#NP (selector)XThe LDT descriptor was marked not present.Stack, #SSXA memory address exceeded the stack segment limit or wasnon-canonical.XA memory address exceeded a data segment limit or wasnon-canonical.XCPL was not 0.XA null data segment was used to reference memory.General protection,#GPInstruction ReferenceLLDT277AMD64 TechnologyExceptionGeneral protection,#GP(selector)Page fault, #PF27824594—Rev.
3.13—July 2007VirtualReal 8086 ProtectedCause of ExceptionXThe source selector did not point into the GDT.XThe descriptor was beyond the GDT limit.XThe descriptor was not an LDT descriptor.XThe descriptor's extended attribute bits were not zero in 64bit mode.XThe new LDT base address was non-canonical.XA page fault resulted from the execution of the instruction.LLDTInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyLMSWLoad Machine Status WordLoads the lower four bits of the 16-bit register or memory operand into bits 3–0 of the machine statusword in register CR0. Only the protection enabled (PE), monitor coprocessor (MP), emulation (EM),and task switched (TS) bits of CR0 are modified.
Additionally, LMSW can set CR0.PE, but cannotclear it.The LMSW instruction can be used only when the current privilege level is 0. It is only provided forcompatibility with early processors.Use the MOV CR0 instruction to load all 32 or 64 bits of CR0.MnemonicOpcodeLMSW reg/mem16DescriptionLoad the lower 4 bits of the source into the lower 4 bits ofCR0.0F 01 /6Related InstructionsMOV (CRn), SMSWrFLAGS AffectedNoneExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXA memory address exceeded the stack segment limit or wasnon-canonical.XXA memory address exceeded a data segment limit or was noncanonical.XCPL was not 0.XA null data segment was used to reference memory.XA page fault resulted from the execution of the instruction.General protection,#GPPage fault, #PFInstruction ReferenceXLMSW279AMD64 Technology24594—Rev.
3.13—July 2007LSLLoad Segment LimitLoads the segment limit from the segment descriptor specified by a 16-bit source register or memoryoperand into a specified 16-bit, 32-bit, or 64-bit general-purpose register and sets the zero (ZF) flag inthe rFLAGS register if successful. LSL clears the zero flag if the descriptor is invalid for any reason.In 64-bit mode, for both 32-bit and 64-bit operand sizes, 32-bit register results are zero-extended to 64bits.The LSL instruction checks that:••the segment selector is not a null selector.the descriptor is within the GDT or LDT limit.•the descriptor DPL is greater than or equal to both the CPL and RPL, or the segment is a conforming code segment.the descriptor type is valid for the LAR instruction.
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