Volume 3 General-Purpose and System Instructions (794097), страница 45
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See Volume 2: System Programming, for information on SMIs.Current privilege level must be 0 to execute this instruction.MnemonicOpcodeHLTDescriptionF4Halt instruction execution.Related InstructionsSTI, CLIrFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GP258VirtualReal 8086 ProtectedXXCause of ExceptionCPL was not 0.HLTInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyINT 3Interrupt to Debug VectorCalls the debug exception handler.
This instruction maps to a 1-byte opcode (CC) that raises a #BPexception. The INT 3 instruction is normally used by debug software to set instruction breakpoints byreplacing the first byte of the instruction opcode bytes with the INT 3 opcode.This one-byte INT 3 instruction behaves differently from the two-byte INT 3 instruction (opcode CD03) (see “INT” in Chapter 3 “General Purpose Instructions” for further information) in two ways:The #BP exception is handled without any IOPL checking in virtual x86 mode. (IOPL mismatches willnot trigger an exception.)•In VME mode, the #BP exception is not redirected via the interrupt redirection table.
(Instead, it ishandled by a protected mode handler.)MnemonicINT 3OpcodeDescriptionCCTrap to debugger at Interrupt 3.For complete descriptions of the steps performed by INT instructions, see the following:••Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” in Volume 2.Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in Volume 2.Action// Refer to INT instruction’s Action section for the details on INT_N_REAL,// INT_N_PROTECTED, and INT_N_VIRTUAL_TO_PROTECTED.INT3_START:If (REAL_MODE)INT_N_REAL//N = 3ELSEIF (PROTECTED_MODE)INT_N_PROTECTED//N = 3ELSE // VIRTUAL_MODEINT_N_VIRTUAL_TO_PROTECTED//N = 3Related InstructionsINT, INTO, IRETInstruction ReferenceINT 3259AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIf a task switch occurs, all flags are modified; otherwise, setting are as follows:ID21VIP20VIF19ACVMRFNTM00M18171614IOPLOF13–1211DF10IFTFM098SFZFAFPFCF76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flagsare blank. Undefined flags are U.ExceptionsExceptionBreakpoint, #BPVirtualReal 8086 ProtectedXXXINT 3 instruction was executed.XXAs part of a stack switch, the target stack segment selector orrSP in the TSS that was beyond the TSS limit.XXAs part of a stack switch, the target stack segment selector inthe TSS was beyond the limit of the GDT or LDT descriptortable.XXAs part of a stack switch, the target stack segment selector inthe TSS was a null selector.XXAs part of a stack switch, the target stack segment selector’sTI bit was set, but the LDT selector was a null selector.XXAs part of a stack switch, the target stack segment selector inthe TSS contained a RPL that was not equal to its DPL.XXAs part of a stack switch, the target stack segment selector inthe TSS contained a DPL that was not equal to the CPL of thecode segment selector.XXAs part of a stack switch, the target stack segment selector inthe TSS was not a writable segment.XXThe accessed code segment, interrupt gate, trap gate, taskgate, or TSS was not present.XXA memory address exceeded the stack segment limit or wasnon-canonical.XXAfter a stack switch, a memory address exceeded the stacksegment limit or was non-canonical and a stack switchoccurred.XXAs part of a stack switch, the SS register was loaded with anon-null segment selector and the segment was marked notpresent.XXXA memory address exceeded the data segment limit or wasnon-canonical.XXXThe target offset exceeded the code segment limit or was noncanonical.Invalid TSS, #TS(selector)Segment notpresent, #NP(selector)Stack, #SSXStack, #SS(selector)General protection,#GP260Cause of ExceptionINT 3Instruction Reference24594—Rev.
3.13—July 2007ExceptionAMD64 TechnologyVirtualReal 8086 ProtectedXGeneral protection,#GP(selector)Cause of ExceptionXXThe interrupt vector was beyond the limit of IDT.XXThe descriptor in the IDT was not an interrupt, trap, or taskgate in legacy mode or not a 64-bit interrupt or trap gate inlong mode.XXThe DPL of the interrupt, trap, or task gate descriptor was lessthan the CPL.XXThe segment selector specified by the interrupt or trap gatehad its TI bit set, but the LDT selector was a null selector.XXThe segment descriptor specified by the interrupt or trap gateexceeded the descriptor table limit or was a null selector.XXThe segment descriptor specified by the interrupt or trap gatewas not a code segment in legacy mode, or not a 64-bit codesegment in long mode.XThe DPL of the segment specified by the interrupt or trap gatewas greater than the CPL.The DPL of the segment specified by the interrupt or trap gatepointed was not 0 or it was a conforming segment.XPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceINT 3261AMD64 Technology24594—Rev.
3.13—July 2007INVDInvalidate CachesInvalidates internal caches (data cache, instruction cache, and on-chip L2 cache) and triggers a buscycle that causes external caches to invalidate themselves as well.No data is written back to main memory from invalidating internal caches. After invalidating internalcaches, the processor proceeds immediately with the execution of the next instruction without waitingfor external hardware to invalidate its caches.This is a privileged instruction.
The current privilege level (CPL) of a procedure invalidating theprocessor’s internal caches must be 0.To insure that data is written back to memory prior to invalidating caches, use the WBINVDinstruction.This instruction does not invalidate TLB caches.INVD is a serializing instruction.MnemonicOpcodeINVDDescriptionInvalidate internal caches and trigger external cacheinvalidations.0F 08Related InstructionsWBINVD, CLFLUSHrFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GP262VirtualReal 8086 ProtectedXXCause of ExceptionCPL was not 0.INVDInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyINVLPGInvalidate TLB EntryInvalidates the TLB entry that would be used for the 1-byte memory operand.This instruction invalidates the TLB entry, regardless of the G (Global) bit setting in the associatedPDE or PTE entry and regardless of the page size (4 Kbytes, 2 Mbytes, or 4 Mbytes).
It may invalidateany number of additional TLB entries, in addition to the targeted entry.INVLPG is a serializing instruction and a privileged instruction. The current privilege level must be 0to execute this instruction.See “Page Translation and Protection” in Volume 2 for more information on page translation.MnemonicINVLPG mem8OpcodeDescriptionInvalidate the TLB entry for the page containing a specifiedmemory location.0F 01 /7Related InstructionsINVLPGA, MOV CRn (CR3 and CR4)rFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedGeneral protection,#GPInstruction ReferenceXXCause of ExceptionCPL was not 0.INVLPG263AMD64 Technology24594—Rev.
3.13—July 2007INVLPGAInvalidate TLB Entry in a Specified ASIDInvalidates the TLB mapping for a given virtual page and a given ASID. The virtual address isspecified in the implicit register operand rAX. The portion of RAX used to form the address isdetermined by the effective address size.
The ASID is taken from ECX.The INVLPGA instruction may invalidate any number of additional TLB entries, in addition to thetargeted entry.The INVLPGA instruction is a serializing instruction and a privileged instruction. The currentprivilege level must be 0 to execute this instruction.This is a Secure Virtual Machine instruction. This instruction generates a #UD exception if SVM isnot enabled. See “Enabling SVM” on page 367 in AMD64 Architecture Programmer’s ManualVolume-2: System Instructions, order# 24593.MnemonicOpcodeINVLPGA rAX, ECXDescriptionInvalidates the TLB mapping for the virtual pagespecified in rAX and the ASID specified in ECX.0F 01 DFRelated InstructionsINVLPG.rFLAGS AffectedNone.ExceptionsExceptionVirtualReal 8086 ProtectedXXInvalid opcode, #UDXGeneral protection,#GP264Cause of ExceptionXThe SVM instructions are not supported as indicated by ECXbit 2 as returned by CPUID function 8000_0001h.XSecure Virtual Machine was not enabled (EFER.SVME=0).XInstruction is only recognized in protected mode.XCPL was not zero.INVLPGAInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyIRETIRETDIRETQReturn from InterruptReturns program control from an exception or interrupt handler to a program or procedure previouslyinterrupted by an exception, an external interrupt, or a software-generated interrupt. These instructionsalso perform a return from a nested task. All flags, CS, and rIP are restored to the values they hadbefore the interrupt so that execution may continue at the next instruction following the interrupt orexception. In 64-bit mode or if the CPL changes, SS and RSP are also restored.IRET, IRETD, and IRETQ are synonyms mapping to the same opcode. They are intended to providesemantically distinct forms for various opcode sizes.
The IRET instruction is used for 16-bit operandsize; IRETD is used for 32-bit operand sizes; IRETQ is used for 64-bit operands. The latter form isonly meaningful in 64-bit mode.IRET, IRETD, or IRETQ must be used to terminate the exception or interrupt handler associated withthe exception, external interrupt, or software-generated interrupt.IRETx is a serializing instruction.For detailed descriptions of the steps performed by IRETx instructions, see the following:••Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” in Volume 2.Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in Volume 2.MnemonicOpcodeDescriptionIRETCFReturn from interrupt (16-bit operand size).IRETDCFReturn from interrupt (32-bit operand size).IRETQCFReturn from interrupt (64-bit operand size).ActionIRET_START:IF (REAL_MODE)IRET_REALELSIF (PROTECTED_MODE)IRET_PROTECTEDELSE // (VIRTUAL_MODE)IRET_VIRTUALIRET_REAL:POP.v temp_RIPPOP.v temp_CSPOP.v temp_RFLAGSInstruction ReferenceIRETx265AMD64 Technology24594—Rev.
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