Volume 3 General-Purpose and System Instructions (794097), страница 44

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Only system instructions canaccess certain processor resources, such as the control registers, model-specific registers, and debugregisters.System instructions are supported in all hardware implementations of the AMD64 architecture, exceptthat the following system instructions are implemented only if their associated CPUID function bitsare set:•••••RDMSR and WRMSR, indicated by bit 5 of CPUID function 0000_0001h or function8000_0001h.SYSENTER and SYSEXIT, indicated by bit 11 of CPUID function 0000_0001h.SYSCALL and SYSRET, indicated by bit 11 of CPUID function 8000_0001h.Long Mode instructions, indicated by bit 29 of CPUID function 8000_0001h.There are also several other CPUID function bits that control the use of system resources andfunctions, such as paging functions, virtual-mode extensions, machine-check exceptions,advanced programmable interrupt control (APIC), memory-type range registers (MTRRs), etc.For details, see “Processor Feature Identification” in Volume 2.For further information about the system instructions and register resources, see:••••“System-Management Instructions” in Volume 2.“Summary of Registers and Data Types” on page 24.“Notation” on page 37.“Instruction Prefixes” on page 3.Instruction Reference251AMD64 Technology24594—Rev.

3.13—July 2007ARPLAdjust Requestor Privilege LevelCompares the requestor privilege level (RPL) fields of two segment selectors in the source anddestination operands of the instruction. If the RPL field of the destination operand is less than the RPLfield of the segment selector in the source register, then the zero flag is set and the RPL field of thedestination operand is increased to match that of the source operand. Otherwise, the destinationoperand remains unchanged and the zero flag is cleared.The destination operand can be either a 16-bit register or memory location; the source operand must bea 16-bit register.The ARPL instruction is intended for use by operating-system procedures to adjust the RPL of asegment selector that has been passed to the operating system by an application program to match theprivilege level of the application program.

The segment selector passed to the operating system isplaced in the destination operand and the segment selector for the code segment of the applicationprogram is placed in the source operand. The RPL field in the source operand represents the privilegelevel of the application program. The ARPL instruction then insures that the RPL of the segmentselector received by the operating system is no lower than the privilege level of the applicationprogram.See “Adjusting Access Rights” in Volume 2, for more information on access rights.In 64-bit mode, this opcode (63H) is used for the MOVSXD instruction.MnemonicOpcodeARPL reg/mem16, reg1663 /rDescriptionAdjust the RPL of a destination segment selector toa level not less than the RPL of the segmentselector specified in the 16-bit source register.(Invalid in 64-bit mode.)Related InstructionsLAR, LSL, VERR, VERW252ARPLInstruction Reference24594—Rev.

3.13—July 2007AMD64 TechnologyrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF420M2120191817161413–1211109876Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flagsare blank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode, #UDStack, #SSXCause of ExceptionThis instruction is only recognized in protected legacy andcompatibility mode.XXA memory address exceeded the stack segment limit.XA memory address exceeded a data segment limit.XThe destination operand was in a non-writable segment.XA null segment selector was used to reference memory.Page fault, #PFXA page fault resulted from the execution of the instruction.Alignment check, #ACXAn unaligned memory reference was performed whilealignment checking was enabled.General protection,#GPInstruction ReferenceARPL253AMD64 Technology24594—Rev. 3.13—July 2007CLGIClear Global Interrupt FlagClears the global interrupt flag (GIF).

While GIF is zero, all external interrupts are disabled.This is a Secure Virtual Machine instruction. This instruction generates a #UD exception if SVM isnot enabled. See “Enabling SVM” on page 367 in AMD64 Architecture Programmer’s ManualVolume-2: System Instructions, order# 24593.MnemonicOpcodeCLGIDescription0F 01 DDClears the global interrupt flag (GIF).Related InstructionsSTGIrFLAGS AffectedNone.ExceptionsExceptionVirtualReal 8086 ProtectedXXInvalid opcode, #UDXGeneral protection,#GP254Cause of ExceptionXThe SVM instructions are not supported as indicated by ECXbit 2 as returned by CPUID function 8000_0001h.XSecure Virtual Machine was not enabled (EFER.SVME=0).XInstruction is only recognized in protected mode.XCPL was not zero.CLGIInstruction Reference24594—Rev.

3.13—July 2007AMD64 TechnologyCLIClear Interrupt FlagClears the interrupt flag (IF) in the rFLAGS register to zero, thereby masking external interruptsreceived on the INTR input. Interrupts received on the non-maskable interrupt (NMI) input are notaffected by this instruction.In real mode, this instruction clears IF to 0.In protected mode and virtual-8086-mode, this instruction is IOPL-sensitive. If the CPL is less than orequal to the rFLAGS.IOPL field, the instruction clears IF to 0.In protected mode, if IOPL < 3, CPL = 3, and protected mode virtual interrupts are enabled (CR4.PVI= 1), then the instruction instead clears rFLAGS.VIF to 0. If none of these conditions apply, theprocessor raises a general-purpose exception (#GP).

For more information, see “Protected ModeVirtual Interrupts” in Volume 2.In virtual-8086 mode, if IOPL < 3 and the virtual-8086-mode extensions are enabled (CR4.VME = 1),the CLI instruction clears the virtual interrupt flag (rFLAGS.VIF) to 0 instead.See “Virtual-8086 Mode Extensions” in Volume 2 for more information about IOPL-sensitiveinstructions.MnemonicCLIOpcodeFADescriptionClear the interrupt flag (IF) to zero.ActionIF (CPL <= IOPL)RFLAGS.IF = 0ELSEIF (((VIRTUAL_MODE) && (CR4.VME = 1))|| ((PROTECTED_MODE) && (CR4.PVI = 1) && (CPL == 3)))RFLAGS.VIF = 0;ELSEEXCEPTION[#GP(0)]Related InstructionsSTIInstruction ReferenceCLI255AMD64 Technology24594—Rev.

3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFM212019IFTFSFZFAFPFCF876420M1817161413–1211109Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flagsare blank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedThe CPL was greater than the IOPL and virtual modeextensions are not enabled (CR4.VME = 0).XGeneral protection,#GP256Cause of ExceptionXThe CPL was greater than the IOPL and either the CPL wasnot 3 or protected mode virtual interrupts were not enabled(CR4.PVI = 0).CLIInstruction Reference24594—Rev.

3.13—July 2007AMD64 TechnologyCLTSClear Task-Switched Flag in CR0Clears the task-switched (TS) flag in the CR0 register to 0. The processor sets the TS flag on each taskswitch. The CLTS instruction is intended to facilitate the synchronization of FPU context saves duringmultitasking operations.This instruction can only be used if the current privilege level is 0.See “System-Control Registers” in Volume 2 for more information on FPU synchronization and theTS flag.MnemonicCLTSOpcodeDescription0F 06Clear the task-switched (TS) flag in CR0 to 0.Related InstructionsLMSW, MOV (CRn)rFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedGeneral protection,#GPInstruction ReferenceXXCause of ExceptionCPL was not 0.CLTS257AMD64 Technology24594—Rev.

3.13—July 2007HLTHaltCauses the microprocessor to halt instruction execution and enter the HALT state. Entering the HALTstate puts the processor in low-power mode. Execution resumes when an unmasked hardware interrupt(INTR), non-maskable interrupt (NMI), system management interrupt (SMI), RESET, or INIT occurs.If an INTR, NMI, or SMI is used to resume execution after a HLT instruction, the saved instructionpointer points to the instruction following the HLT instruction.Before executing a HLT instruction, hardware interrupts should be enabled. If rFLAGS.IF = 0, thesystem will remain in a HALT state until an NMI, SMI, RESET, or INIT occurs.If an SMI brings the processor out of the HALT state, the SMI handler can decide whether to return tothe HALT state or not.

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