Volume 3 General-Purpose and System Instructions (794097), страница 43
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3.13—July 2007AMD64 TechnologyXCHGExchangeExchanges the contents of the two operands. The operands can be two general-purpose registers or aregister and a memory location. If either operand references memory, the processor locksautomatically, whether or not the LOCK prefix is used and independently of the value of IOPL. Fordetails about the LOCK prefix, see “Lock Prefix” on page 8.The x86 architecture commonly uses the XCHG EAX, EAX instruction (opcode 90h) as a one-byteNOP.
In 64-bit mode, the processor treats opcode 90h as a true NOP only if it would exchange rAXwith itself. Without this special handling, the instruction would zero-extend the upper 32 bits of RAX,and thus it would not be a true no-operation. Opcode 90h can still be used to exchange rAX and r8 ifthe appropriate REX prefix is used.This special handling does not apply to the two-byte ModRM form of the XCHG instruction.MnemonicOpcodeDescriptionXCHG AX, reg1690 +rwExchange the contents of the AX register with thecontents of a 16-bit register.XCHG reg16, AX90 +rwExchange the contents of a 16-bit register with thecontents of the AX register.XCHG EAX, reg3290 +rdExchange the contents of the EAX register with thecontents of a 32-bit register.XCHG reg32, EAX90 +rdExchange the contents of a 32-bit register with thecontents of the EAX register.XCHG RAX, reg6490 +rqExchange the contents of the RAX register with thecontents of a 64-bit register.XCHG reg64, RAX90 +rqExchange the contents of a 64-bit register with thecontents of the RAX register.XCHG reg/mem8, reg886 /rExchange the contents of an 8-bit register with thecontents of an 8-bit register or memory operand.XCHG reg8, reg/mem886 /rExchange the contents of an 8-bit register or memoryoperand with the contents of an 8-bit register.XCHG reg/mem16, reg1687 /rExchange the contents of a 16-bit register with thecontents of a 16-bit register or memory operand.XCHG reg16, reg/mem1687 /rExchange the contents of a 16-bit register or memoryoperand with the contents of a 16-bit register.XCHG reg/mem32, reg3287 /rExchange the contents of a 32-bit register with thecontents of a 32-bit register or memory operand.XCHG reg32, reg/mem3287 /rExchange the contents of a 32-bit register or memoryoperand with the contents of a 32-bit register.XCHG reg/mem64, reg6487 /rExchange the contents of a 64-bit register with thecontents of a 64-bit register or memory operand.XCHG reg64, reg/mem6487 /rExchange the contents of a 64-bit register or memoryoperand with the contents of a 64-bit register.Instruction ReferenceXCHG245AMD64 Technology24594—Rev.
3.13—July 2007Related InstructionsBSWAP, XADDrFLAGS AffectedNoneExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe source or destination operand was in a non-writablesegment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.246XCHGInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyXLATXLATBTranslate Table IndexUses the unsigned integer in the AL register as an offset into a table and copies the contents of the tableentry at that location to the AL register.The instruction uses seg:[rBX] as the base address of the table. The value of seg defaults to the DSsegment, but may be overridden by a segment prefix.This instruction writes AL without changing RAX[63:8].
This instruction ignores operand size.The single-operand form of the XLAT instruction uses the operand to document the segment andaddress size attribute, but it uses the base address specified by the rBX register.This instruction is often used to translate data from one format (such as ASCII) to another (such asEBCDIC).MnemonicOpcodeDescriptionXLAT mem8D7Set AL to the contents of DS:[rBX + unsigned AL].XLATBD7Set AL to the contents of DS:[rBX + unsigned AL].Related InstructionsNonerFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.XA page fault resulted from the execution of the instruction.Page fault, #PFXGeneral-Purpose Instruction Reference247AMD64 Technology24594—Rev.
3.13—July 2007XORLogical Exclusive ORPerforms a bitwise exclusive OR operation on both operands and stores the result in the first operandlocation. The first operand can be a register or memory location. The second operand can be animmediate value, a register, or a memory location. XOR-ing a register with itself clears the register.The forms of the XOR instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.The instruction performs the following operation for each bit:XYX XOR Y000011101110MnemonicOpcodeDescriptionXOR AL, imm834 ibXOR the contents of AL with an immediate 8-bitoperand and store the result in AL.XOR AX, imm1635 iwXOR the contents of AX with an immediate 16-bitoperand and store the result in AX.XOR EAX, imm3235 idXOR the contents of EAX with an immediate 32-bitoperand and store the result in EAX.XOR RAX, imm3235 idXOR the contents of RAX with a sign-extendedimmediate 32-bit operand and store the result in RAX.XOR reg/mem8, imm880 /6 ibXOR the contents of an 8-bit destination register ormemory operand with an 8-bit immediate value andstore the result in the destination.XOR reg/mem16, imm1681 /6 iwXOR the contents of a 16-bit destination register ormemory operand with a 16-bit immediate value andstore the result in the destination.XOR reg/mem32, imm3281 /6 idXOR the contents of a 32-bit destination register ormemory operand with a 32-bit immediate value andstore the result in the destination.XOR reg/mem64, imm3281 /6 idXOR the contents of a 64-bit destination register ormemory operand with a sign-extended 32-bit immediatevalue and store the result in the destination.XOR reg/mem16, imm883 /6 ibXOR the contents of a 16-bit destination register ormemory operand with a sign-extended 8-bit immediatevalue and store the result in the destination.248General-Purpose Instruction Reference24594—Rev.
3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionXOR reg/mem32, imm883 /6 ibXOR the contents of a 32-bit destination register ormemory operand with a sign-extended 8-bit immediatevalue and store the result in the destination.XOR reg/mem64, imm883 /6 ibXOR the contents of a 64-bit destination register ormemory operand with a sign-extended 8-bit immediatevalue and store the result in the destination.XOR reg/mem8, reg830 /rXOR the contents of an 8-bit destination register ormemory operand with the contents of an 8-bit registerand store the result in the destination.XOR reg/mem16, reg1631 /rXOR the contents of a 16-bit destination register ormemory operand with the contents of a 16-bit registerand store the result in the destination.XOR reg/mem32, reg3231 /rXOR the contents of a 32-bit destination register ormemory operand with the contents of a 32-bit registerand store the result in the destination.XOR reg/mem64, reg6431 /rXOR the contents of a 64-bit destination register ormemory operand with the contents of a 64-bit registerand store the result in the destination.XOR reg8, reg/mem832 /rXOR the contents of an 8-bit destination register withthe contents of an 8-bit register or memory operand andstore the results in the destination.XOR reg16, reg/mem1633 /rXOR the contents of a 16-bit destination register withthe contents of a 16-bit register or memory operand andstore the results in the destination.XOR reg32, reg/mem3233 /rXOR the contents of a 32-bit destination register withthe contents of a 32-bit register or memory operand andstore the results in the destination.XOR reg64, reg/mem6433 /rXOR the contents of a 64-bit destination register withthe contents of a 64-bit register or memory operand andstore the results in the destination.Related InstructionsOR, AND, NOT, NEGGeneral-Purpose Instruction Reference249AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTF02120191817161413–12111098SFZFAFPFCFMMUM076420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.250General-Purpose Instruction Reference24594—Rev. 3.13—July 20074AMD64 TechnologySystem Instruction ReferenceThis chapter describes the function, mnemonic syntax, opcodes, affected flags, and possibleexceptions generated by the system instructions.
The system instructions are used to establish theoperating mode, access processor resources, handle program and system errors, and manage memory.Many of these instructions can only be executed by privileged software, such as the operating systemkernel and interrupt handlers, that run at the highest privilege level.
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