Volume 3 General-Purpose and System Instructions (794097), страница 38
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For 1-bit rotates, the instruction sets the OF flag to the exclusive OR of thetwo most significant bits of the result. When the rotate count is greater than 1, the OF flag is undefined.When the rotate count is 0, no flags are affected.MnemonicOpcodeDescriptionROR reg/mem8, 1D0 /1Rotate an 8-bit register or memory location right 1 bit.ROR reg/mem8, CLD2 /1Rotate an 8-bit register or memory location right thenumber of bits specified in the CL register.ROR reg/mem8, imm8C0 /1 ibRotate an 8-bit register or memory location right thenumber of bits specified by an 8-bit immediate value.ROR reg/mem16, 1D1 /1Rotate a 16-bit register or memory location right 1 bit.ROR reg/mem16, CLD3 /1Rotate a 16-bit register or memory location right thenumber of bits specified in the CL register.ROR reg/mem16, imm8C1 /1 ibRotate a 16-bit register or memory location right thenumber of bits specified by an 8-bit immediate value.ROR reg/mem32, 1D1 /1Rotate a 32-bit register or memory location right 1 bit.ROR reg/mem32, CLD3 /1Rotate a 32-bit register or memory location right thenumber of bits specified in the CL register.ROR reg/mem32, imm8C1 /1 ibRotate a 32-bit register or memory location right thenumber of bits specified by an 8-bit immediate value.ROR reg/mem64, 1D1 /1Rotate a 64-bit register or memory location right 1 bit.ROR reg/mem64, CLD3 /1Rotate a 64-bit register or memory operand right thenumber of bits specified in the CL register.ROR reg/mem64, imm8C1 /1 ibRotate a 64-bit register or memory operand right thenumber of bits specified by an 8-bit immediate value.Related InstructionsRCL, RCR, ROLInstruction ReferenceROR213AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFM2120191817161413–1211CFM109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.214RORInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologySAHFStore AH into FlagsLoads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the correspondingbits in the AH register (bits 7, 6, 4, 2, and 0, respectively). The instruction ignores bits 1, 3, and 5 ofregister AH; it sets those bits in the EFLAGS register to 1, 0, and 0, respectively.The SAHF instruction can only be executed in 64-bit mode if supported by the processorimplementation. Check the status of ECX bit 0 returned by CPUID function 8000_0001h to verify thatthe processor supports SAHF in 64-bit mode.MnemonicOpcodeSAHFDescriptionLoads the sign flag, the zero flag, the auxiliary flag, theparity flag, and the carry flag from the AH register intothe lower 8 bits of the EFLAGS register.9ERelated InstructionsLAHFrFLAGS AffectedID21VIP20VIF19AC18VM17RF16NT14IOPLOF13–1211DF10IF9TF8SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode, #UDInstruction ReferenceXCause of ExceptionThis instruction is not supported in 64-bit mode, as indicatedby ECX bit 0 returned by CPUID function 8000_0001h.SAHF215AMD64 Technology24594—Rev. 3.13—July 2007SALSHLShift LeftShifts the bits of a register or memory location (first operand) to the left through the CF bit by thenumber of bit positions in an unsigned immediate value or the CL register (second operand). Theinstruction discards bits shifted out of the CF flag.
For each bit shift, the SAL instruction clears theleast-significant bit to 0. At the end of the shift operation, the CF flag contains the last bit shifted out ofthe first operand.The processor masks the upper three bits of the count operand, thus restricting the count to a numberbetween 0 and 31. When the destination is 64 bits wide, the processor masks the upper two bits of thecount, providing a count in the range of 0 to 63.The effect of this instruction is multiplication by powers of two.For 1-bit shifts, the instruction sets the OF flag to the exclusive OR of the CF bit (after the shift) andthe most significant bit of the result.
When the shift count is greater than 1, the OF flag is undefined.If the shift count is 0, no flags are modified.SHL is an alias to the SAL instruction.MnemonicOpcodeDescriptionSAL reg/mem8, 1D0 /4Shift an 8-bit register or memory location left 1 bit.SAL reg/mem8, CLD2 /4Shift an 8-bit register or memory location left the numberof bits specified in the CL register.SAL reg/mem8, imm8C0 /4 ibShift an 8-bit register or memory location left the numberof bits specified by an 8-bit immediate value.SAL reg/mem16, 1D1 /4Shift a 16-bit register or memory location left 1 bit.SAL reg/mem16, CLD3 /4Shift a 16-bit register or memory location left the numberof bits specified in the CL register.SAL reg/mem16, imm8C1 /4 ibShift a 16-bit register or memory location left the numberof bits specified by an 8-bit immediate value.SAL reg/mem32, 1D1 /4Shift a 32-bit register or memory location left 1 bit.SAL reg/mem32, CLD3 /4Shift a 32-bit register or memory location left the numberof bits specified in the CL register.SAL reg/mem32, imm8C1 /4 ibShift a 32-bit register or memory location left the numberof bits specified by an 8-bit immediate value.SAL reg/mem64, 1D1 /4Shift a 64-bit register or memory location left 1 bit.SAL reg/mem64, CLD3 /4Shift a 64-bit register or memory location left the numberof bits specified in the CL register.SAL reg/mem64, imm8C1 /4 ibShift a 64-bit register or memory location left the numberof bits specified by an 8-bit immediate value.216SAL, SHLInstruction Reference24594—Rev.
3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionSHL reg/mem8, 1D0 /4Shift an 8-bit register or memory location by 1 bit.SHL reg/mem8, CLD2 /4Shift an 8-bit register or memory location left the numberof bits specified in the CL register.SHL reg/mem8, imm8C0 /4 ibShift an 8-bit register or memory location left the numberof bits specified by an 8-bit immediate value.SHL reg/mem16, 1D1 /4Shift a 16-bit register or memory location left 1 bit.SHL reg/mem16, CLD3 /4Shift a 16-bit register or memory location left the numberof bits specified in the CL register.SHL reg/mem16, imm8C1 /4 ibShift a 16-bit register or memory location left the numberof bits specified by an 8-bit immediate value.SHL reg/mem32, 1D1 /4Shift a 32-bit register or memory location left 1 bit.SHL reg/mem32, CLD3 /4Shift a 32-bit register or memory location left the numberof bits specified in the CL register.SHL reg/mem32, imm8C1 /4 ibShift a 32-bit register or memory location left the numberof bits specified by an 8-bit immediate value.SHL reg/mem64, 1D1 /4Shift a 64-bit register or memory location left 1 bit.SHL reg/mem64, CLD3 /4Shift a 64-bit register or memory location left the numberof bits specified in the CL register.SHL reg/mem64, imm8C1 /4 ibShift a 64-bit register or memory location left the numberof bits specified by an 8-bit immediate value.Related InstructionsSAR, SHR, SHLD, SHRDrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMUMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.Instruction ReferenceSAL, SHL217AMD64 Technology24594—Rev. 3.13—July 2007ExceptionsExceptionVirtualReal 8086 ProtectedStack, #SSXCause of ExceptionXXA memory address exceeded the stack segment limit or wasnon-canonical.XXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.218SAL, SHLInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologySARShift Arithmetic RightShifts the bits of a register or memory location (first operand) to the right through the CF bit by thenumber of bit positions in an unsigned immediate value or the CL register (second operand). Theinstruction discards bits shifted out of the CF flag. At the end of the shift operation, the CF flagcontains the last bit shifted out of the first operand.The SAR instruction does not change the sign bit of the target operand. For each bit shift, it copies thesign bit to the next bit, preserving the sign of the result.The processor masks the upper three bits of the count operand, thus restricting the count to a numberbetween 0 and 31.
When the destination is 64 bits wide, the processor masks the upper two bits of thecount, providing a count in the range of 0 to 63.For 1-bit shifts, the instruction clears the OF flag to 0. When the shift count is greater than 1, the OFflag is undefined.If the shift count is 0, no flags are modified.Although the SAR instruction effectively divides the operand by a power of 2, the behavior is differentfrom the IDIV instruction. For example, shifting –11 (FFFFFFF5h) by two bits to the right (that is,divide –11 by 4), gives a result of FFFFFFFDh, or –3, whereas the IDIV instruction for dividing –11 by4 gives a result of –2. This is because the IDIV instruction rounds off the quotient to zero, whereas theSAR instruction rounds off the remainder to zero for positive dividends and to negative infinity fornegative dividends.
So, for positive operands, SAR behaves like the corresponding IDIV instruction.For negative operands, it gives the same result if and only if all the shifted-out bits are zeroes;otherwise, the result is smaller by 1.MnemonicOpcodeDescriptionSAR reg/mem8, 1D0 /7Shift a signed 8-bit register or memory operand right 1bit.SAR reg/mem8, CLD2 /7Shift a signed 8-bit register or memory operand right thenumber of bits specified in the CL register.SAR reg/mem8, imm8C0 /7 ibShift a signed 8-bit register or memory operand right thenumber of bits specified by an 8-bit immediate value.SAR reg/mem16, 1D1 /7Shift a signed 16-bit register or memory operand right 1bit.SAR reg/mem16, CLD3 /7Shift a signed 16-bit register or memory operand rightthe number of bits specified in the CL register.SAR reg/mem16, imm8C1 /7 ibShift a signed 16-bit register or memory operand rightthe number of bits specified by an 8-bit immediate value.SAR reg/mem32, 1D1 /7Shift a signed 32-bit register or memory location 1 bit.SAR reg/mem32, CLD3 /7Shift a signed 32-bit register or memory location rightthe number of bits specified in the CL register.Instruction ReferenceSAR219AMD64 Technology24594—Rev.
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