Volume 3 General-Purpose and System Instructions (794097), страница 37
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3.13—July 2007AMD64 TechnologyRET (Far)Far Return from Called ProcedureReturns from a procedure previously entered by a CALL Far instruction. This form of the RETinstruction returns to a calling procedure in a different segment than the current code segment. It canreturn to the same CPL or to a less privileged CPL.RET Far pops a target CS and rIP from the stack. If the new code segment is less privileged than thecurrent code segment, the stack pointer is incremented by the number of bytes indicated by theimmediate operand, if present; then a new SS and rSP are also popped from the stack.The final value of rSP is incremented by the number of bytes indicated by the immediate operand, ifpresent.
This action skips over the parameters (previously passed to the subroutine) that are no longerneeded.All stack pops are determined by the operand size. If necessary, the target rIP is zero-extended to 64bits before assuming program control.If the CPL changes, the data segment selectors are set to NULL for any of the data segments (DS, ES,FS, GS) not accessible at the new CPL.See RET (Near) for information on near returns—returns to procedures located inside the current codesegment. For details about control-flow instructions, see “Control Transfers” in Volume 1, and“Control-Transfer Privilege Checks” in Volume 2.MnemonicOpcodeDescriptionRETFCBFar return to the calling procedure.RETF imm16CA iwFar return to the calling procedure, then pop thespecified number of bytes from the stack.Action// Far returns (RETF)// See “Pseudocode Definitions” on page 41.RETF_START:IF (REAL_MODE)RETF_REAL_OR_VIRTUALELSIF (PROTECTED_MODE)RETF_PROTECTEDELSE // (VIRTUAL_MODE)RETF_REAL_OR_VIRTUALRETF_REAL_OR_VIRTUAL:IF (OPCODE = retf imm16)temp_IMM = word-sized immediate specified in the instruction,zero-extended to 64 bitsInstruction ReferenceRET (Far)207AMD64 Technology24594—Rev.
3.13—July 2007ELSE // (OPCODE = retf)temp_IMM = 0POP.v temp_RIPPOP.v temp_CSIF (temp_RIP > CS.limit)EXCEPTION [#GP(0)]CS.sel = temp_CSCS.base = temp_CS SHL 4RSP.s = RSP + temp_IMMRIP = temp_RIPEXITRETF_PROTECTED:IF (OPCODE = retf imm16)temp_IMM = word-sized immediate specified in the instruction,zero-extended to 64 bitsELSE // (OPCODE = retf)temp_IMM = 0POP.v temp_RIPPOP.v temp_CStemp_CPL = temp_CS.rplIF (CPL=temp_CPL){CS = READ_DESCRIPTOR (temp_CS, iret_chk)RSP.s = RSP + temp_IMMIF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit))EXCEPTION [#GP(0)]RIP = temp_RIPEXIT}ELSE // (CPL!=temp_CPL){RSP.s = RSP + temp_IMMPOP.v temp_RSPPOP.v temp_SSCS = READ_DESCRIPTOR (temp_CS, iret_chk)208RET (Far)Instruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyCPL = temp_CPLIF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit))EXCEPTION [#GP(0)]SS = READ_DESCRIPTOR (temp_SS, ss_chk)RSP.s = temp_RSP + temp_IMMIF (changing CPL){FOR (seg = ES, DS, FS, GS)IF ((seg.attr.dpl < CPL) && ((seg.attr.type = ’data’)|| (seg.attr.type = ’non-conforming-code’))){seg = NULL // can’t use lower dpl data segment at higher cpl}}RIP = temp_RIPEXIT}Related InstructionsCALL (Near), CALL (Far), RET (Near)rFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedSegment notpresent, #NP(selector)Stack, #SSXXStack, #SS(selector)General protection,#GPXInstruction ReferenceXCause of ExceptionXThe return code segment was marked not present.XA memory address exceeded the stack segment limit or wasnon-canonical.XThe return stack segment was marked not present.XThe target offset exceeded the code segment limit or was noncanonical.RET (Far)209AMD64 TechnologyException24594—Rev.
3.13—July 2007VirtualReal 8086 ProtectedGeneral protection,#GP(selector)Cause of ExceptionXThe return code selector was a null selector.XThe return stack selector was a null selector and the returnmode was non-64-bit mode or CPL was 3.XThe return code or stack descriptor exceeded the descriptortable limit.XThe return code or stack selector’s TI bit was set but the LDTselector was a null selector.XThe segment descriptor for the return code was not a codesegment.XThe RPL of the return code segment selector was less thanthe CPL.XThe return code segment was non-conforming and thesegment selector’s DPL was not equal to the RPL of the codesegment’s segment selector.XThe return code segment was conforming and the segmentselector’s DPL was greater than the RPL of the codesegment’s segment selector.XThe segment descriptor for the return stack was not a writabledata segment.XThe stack segment descriptor DPL was not equal to the RPLof the return code segment selector.XThe stack segment selector RPL was not equal to the RPL ofthe return code segment selector.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned-memory reference was performed whilealignment checking was enabled.210RET (Far)Instruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyROLRotate LeftRotates the bits of a register or memory location (first operand) to the left (toward the more significantbit positions) by the number of bit positions in an unsigned immediate value or the CL register (secondoperand). The bits rotated out left are rotated back in at the right end (lsb) of the first operand location.The processor masks the upper three bits of the count operand, thus restricting the count to a numberbetween 0 and 31. When the destination is 64 bits wide, it masks the upper two bits of the count,providing a count in the range of 0 to 63.After completing the rotation, the instruction sets the CF flag to the last bit rotated out (the lsb of theresult). For 1-bit rotates, the instruction sets the OF flag to the exclusive OR of the CF bit (after therotate) and the most significant bit of the result.
When the rotate count is greater than 1, the OF flag isundefined. When the rotate count is 0, no flags are affected.MnemonicOpcodeDescriptionROL reg/mem8, 1D0 /0Rotate an 8-bit register or memory operand left 1 bit.ROL reg/mem8, CLD2 /0Rotate an 8-bit register or memory operand left thenumber of bits specified in the CL register.ROL reg/mem8, imm8C0 /0 ibRotate an 8-bit register or memory operand left thenumber of bits specified by an 8-bit immediate value.ROL reg/mem16, 1D1 /0Rotate a 16-bit register or memory operand left 1 bit.ROL reg/mem16, CLD3 /0Rotate a 16-bit register or memory operand left thenumber of bits specified in the CL register.ROL reg/mem16, imm8C1 /0 ibRotate a 16-bit register or memory operand left thenumber of bits specified by an 8-bit immediate value.ROL reg/mem32, 1D1 /0Rotate a 32-bit register or memory operand left 1 bit.ROL reg/mem32, CLD3 /0Rotate a 32-bit register or memory operand left thenumber of bits specified in the CL register.ROL reg/mem32, imm8C1 /0 ibRotate a 32-bit register or memory operand left thenumber of bits specified by an 8-bit immediate value.ROL reg/mem64, 1D1 /0Rotate a 64-bit register or memory operand left 1 bit.ROL reg/mem64, CLD3 /0Rotate a 64-bit register or memory operand left thenumber of bits specified in the CL register.ROL reg/mem64, imm8C1 /0 ibRotate a 64-bit register or memory operand left thenumber of bits specified by an 8-bit immediate value.Related InstructionsRCL, RCR, RORInstruction ReferenceROL211AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFM2120191817161413–1211CFM109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.212ROLInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyRORRotate RightRotates the bits of a register or memory location (first operand) to the right (toward the less significantbit positions) by the number of bit positions in an unsigned immediate value or the CL register (secondoperand). The bits rotated out right are rotated back in at the left end (the most significant bit) of thefirst operand location.The processor masks the upper three bits of the count operand, thus restricting the count to a numberbetween 0 and 31. When the destination is 64 bits wide, the processor masks the upper two bits of thecount, providing a count in the range of 0 to 63.After completing the rotation, the instruction sets the CF flag to the last bit rotated out (the mostsignificant bit of the result).
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