Volume 3 General-Purpose and System Instructions (794097), страница 34
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3.13—July 2007AMD64 TechnologyPOPAPOPADPOP All GPRsPops words or doublewords from the stack into the general-purpose registers in the following order:eDI, eSI, eBP, eSP (image is popped and discarded), eBX, eDX, eCX, and eAX. The instructionincrements the stack pointer by 16 or 32, depending on the operand size.Using the POPA or POPAD instructions in 64-bit mode generates an invalid-opcode exception.MnemonicOpcodeDescriptionPOPA61Pop the DI, SI, BP, SP, BX, DX, CX, and AX registers.(Invalid in 64-bit mode.)POPAD61Pop the EDI, ESI, EBP, ESP, EBX, EDX, ECX, and EAXregisters.(Invalid in 64-bit mode.)Related InstructionsPUSHA, PUSHADrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode(#UD)Cause of ExceptionXThis instruction was executed in 64-bit mode.XXA memory address exceeded the stack segment limit.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Stack, #SSXInstruction ReferencePOPAx187AMD64 Technology24594—Rev.
3.13—July 2007POPCNTBit Population CountCounts the number of bits having a value of 1 in the source operand and places the result in thedestination register. The source operand is a 16-, 32-, or 64-bit general purpose register or memoryoperand; the destination operand is a general purpose register of the same size as the source operandregister.If the input operand is zero, the ZF flag is set to 1 and zero is written to the destination register.Otherwise, the ZF flag is cleared. The other flags are cleared.Support for the POPCNT instruction is indicated by ECX bit 23 (POPCNT) as returned by CPUIDfunction 0000_0001h.
Software MUST check the CPUID bit once per program or library initializationbefore using the POPCNT instruction, or inconsistent behavior may result.MnemonicOpcodeDescriptionPOPCNTreg16, reg/mem16F3 0F B8 /rCount the 1s in reg/mem16.POPCNTreg32, reg/mem32F3 0F B8 /rCount the 1s in reg/mem32.POPCNTreg64, reg/mem64F3 0F B8 /rCount the 1s in reg/mem64.Related InstructionsBSF, BSR, LZCNTrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTF02120191817161413–12111098SFZFAFPFCF0M00076420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.188POPCNTInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionInvalid opcode, #UDXXXThe POPCNT instruction is not supported, as indicated byECX bit 23 as returned by CPUID function 0000_0001h.Stack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferencePOPCNT189AMD64 Technology24594—Rev.
3.13—July 2007POPFPOPFDPOPFQPOP to rFLAGSPops a word, doubleword, or quadword from the stack into the rFLAGS register and then incrementsthe stack pointer by 2, 4, or 8, depending on the operand size.In protected or real mode, all the non-reserved flags in the rFLAGS register can be modified, exceptthe VIP, VIF, and VM flags, which are unchanged. In protected mode, at a privilege level greater than0 the IOPL is also unchanged.
The instruction alters the interrupt flag (IF) only when the CPL is lessthan or equal to the IOPL.In virtual-8086 mode, if IOPL field is less than 3, attempting to execute a POPFx or PUSHFxinstruction while VME is not enabled, or the operand size is not 16-bit, generates a #GP exception.In 64-bit mode, this instruction defaults to a 64-bit operand size; there is no prefix available to encodea 32-bit operand size.MnemonicOpcodeDescriptionPOPF9DPop a word from the stack into the FLAGS register.POPFD9DPop a double word from the stack into the EFLAGSregister.
(No prefix for encoding this in 64-bit mode.)POPFQ9DPop a quadword from the stack to the RFLAGS register.Action// See “Pseudocode Definitions” on page 41.POPF_START:IF (REAL_MODE)POPF_REALELSIF (PROTECTED_MODE)POPF_PROTECTEDELSE // (VIRTUAL_MODE)POPF_VIRTUALPOPF_REAL:POP.v temp_RFLAGSRFLAGS.v = temp_RFLAGS// VIF,VIP,VM unchanged// RF clearedEXITPOPF_PROTECTED:190POPFxInstruction Reference24594—Rev. 3.13—July 2007POP.v temp_RFLAGSRFLAGS.v = temp_RFLAGSAMD64 Technology////////VIF,VIP,VM unchangedIOPL changed only if (CPL=0)IF changed only if (CPL<=old_RFLAGS.IOPL)RF clearedEXITPOPF_VIRTUAL:IF (RFLAGS.IOPL=3){POP.v temp_RFLAGSRFLAGS.v = temp_RFLAGS// VIF,VIP,VM,IOPL unchanged// RF clearedEXIT}ELSIF ((CR4.VME=1) && (OPERAND_SIZE=16)){POP.w temp_RFLAGSIF (((temp_RFLAGS.IF=1) && (RFLAGS.VIP=1)) || (temp_RFLAGS.TF=1))EXCEPTION [#GP(0)]// notify the virtual-mode-manager to deliver// the task’s pending interruptsRFLAGS.w = temp_RFLAGS// IF,IOPL unchanged// RFLAGS.VIF=temp_RFLAGS.IF// RF clearedEXIT}ELSE // ((RFLAGS.IOPL<3) && ((CR4.VME=0) || (OPERAND_SIZE!=16)))EXCEPTION [#GP(0)]Related InstructionsPUSHF, PUSHFD, PUSHFQInstruction ReferencePOPFx191AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPM2120VIFACMM1918VM17RFNTIOPLOFDFIFTFSFZFAFPFCF0MMMMMMMMMMM161413–1211109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedXXXCause of ExceptionA memory address exceeded the stack segment limit or wasnon-canonical.The I/O privilege level was less than 3 and one of the followingconditions was true:• CR4.VME was 0.• The effective operand size was 32-bit.• Both the original EFLAGS.VIP and the new EFLAGS.IF bitswere set.• The new EFLAGS.TF bit was set.General protection,#GPXPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.192POPFxInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyPREFETCHPREFETCHWPrefetch L1 Data-Cache LineLoads the entire 64-byte aligned memory sequence containing the specified memory address into theL1 data cache. The position of the specified memory address within the 64-byte cache line isirrelevant. If a cache hit occurs, or if a memory fault is detected, no bus cycle is initiated and theinstruction is treated as a NOP.The PREFETCHW instruction loads the prefetched line and sets the cache-line state to Modified, inanticipation of subsequent data writes to the line.
The PREFETCH instruction, by contrast, typicallysets the cache-line state to Exclusive (depending on the hardware implementation).The opcodes for the PREFETCH/PREFETCHW instructions include the ModRM byte; however, onlythe memory form of ModRM is valid. The register form of ModRM causes an invalid-opcodeexception. Because there is no destination register, the three destination register field bits of theModRM byte define the type of prefetch to be performed.
The bit patterns 000b and 001b define thePREFETCH and PREFETCHW instructions, respectively. All other bit patterns are reserved for futureuse.The reserved PREFETCH types do not result in an invalid-opcode exception if executed. Instead, forforward compatibility with future processors that may implement additional forms of the PREFETCHinstruction, all reserved PREFETCH types are implemented as synonyms of the basic PREFETCHtype (the PREFETCH instruction with type 000b).The operation of these instructions is implementation-dependent. The processor implementation canignore or change these instructions. The size of the cache line also depends on the implementation,with a minimum size of 32 bytes.
For details on the use of this instruction, see the processor data sheetsor other software-optimization documentation relating to particular hardware implementations.Support for these instructions may be indicated by any of the following:•••EDX bit 31 as returned by CPUID function 8000_0001hEDX bit 29 as returned by CPUID function 8000_0001hECX bit 8 as returned by CPUID function 8000_0001hMnemonicOpcodeDescriptionPREFETCH mem80F 0D /0Prefetch processor cache line into L1 data cache.PREFETCHW mem80F 0D /1Prefetch processor cache line into L1 data cache andmark it modified.Related InstructionsPREFETCHlevelInstruction ReferencePREFETCHx193AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedNoneExceptionsException (vector)Invalid opcode, #UD194RealVirtual8086 ProtectedCause of ExceptionXXXThe PREFETCH/W instructions are not supported, asindicated when the following bits are all clear:• PREFETCH/PREFETCHW are not supported, asindicated by ECX bit 8 of CPUID function8000_0001h• Long Mode is not supported, as indicated by EDXbit 29 of CPUID function 8000_0001h• The 3DNow!™ instructions are not supported, asindicated by EDX bit 31 of CPUID function8000_0001h.XXXThe operand was a register.PREFETCHxInstruction Reference24594—Rev.
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