Volume 3 General-Purpose and System Instructions (794097), страница 29
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3.13—July 2007AMD64 TechnologyLEALoad Effective AddressComputes the effective address of a memory location (second operand) and stores it in a generalpurpose register (first operand).The address size of the memory location and the size of the register determine the specific action takenby the instruction, as follows:•••If the address size and the register size are the same, the instruction stores the effective address ascomputed.If the address size is longer than the register size, the instruction truncates the effective address tothe size of the register.If the address size is shorter than the register size, the instruction zero-extends the effective addressto the size of the register.If the second operand is a register, an undefined-opcode exception occurs.The LEA instruction is related to the MOV instruction, which copies data from a memory location to aregister, but LEA takes the address of the source operand, whereas MOV takes the contents of thememory location specified by the source operand.
In the simplest cases, LEA can be replaced withMOV. For example:lea eax, [ebx]has the same effect as:mov eax, ebxHowever, LEA allows software to use any valid ModRM and SIB addressing mode for the sourceoperand. For example:lea eax, [ebx+edi]loads the sum of the EBX and EDI registers into the EAX register. This could not be accomplished bya single MOV instruction.The LEA instruction has a limited capability to perform multiplication of operands in general-purposeregisters using scaled-index addressing. For example:lea eax, [ebx+ebx*8]loads the value of the EBX register, multiplied by 9, into the EAX register. Possible values ofmultipliers are 2, 4, 8, 3, 5, and 9.The LEA instruction is widely used in string-processing and array-processing to initialize an indexregister (rSI or rDI) before performing string instructions such as MOVSx. It is also used to initializethe rBX register before performing the XLAT instruction in programs that perform charactertranslations.
In data structures, the LEA instruction can calculate addresses of operands stored inmemory, and in particular, addresses of array or string elements.Instruction ReferenceLEA145AMD64 Technology24594—Rev. 3.13—July 2007MnemonicOpcodeDescriptionLEA reg16, mem8D /rStore effective address in a 16-bit register.LEA reg32, mem8D /rStore effective address in a 32-bit register.LEA reg64, mem8D /rStore effective address in a 64-bit register.Related InstructionsMOVrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UD146VirtualReal 8086 ProtectedXXXCause of ExceptionThe source operand was a register.LEAInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyLEAVEDelete Procedure Stack FrameReleases a stack frame created by a previous ENTER instruction.
To release the frame, it copies theframe pointer (in the rBP register) to the stack pointer register (rSP), and then pops the old framepointer from the stack into the rBP register, thus restoring the stack frame of the calling procedure.The 32-bit LEAVE instruction is equivalent to the following 32-bit operation:MOV ESP,EBPPOP EBPTo return program control to the calling procedure, execute a RET instruction after the LEAVEinstruction.In 64-bit mode, the LEAVE operand size defaults to 64 bits, and there is no prefix available forencoding a 32-bit operand size.MnemonicOpcodeDescriptionLEAVEC9Set the stack pointer register SP to the value in the BPregister and pop BP.LEAVEC9Set the stack pointer register ESP to the value in theEBP register and pop EBP.(No prefix for encoding this in 64-bit mode.)LEAVEC9Set the stack pointer register RSP to the value in theRBP register and pop RBP.Related InstructionsENTERrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionXXA memory address exceeded the stack segment limit or wasnon-canonical.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Stack, #SSXInstruction ReferenceLEAVE147AMD64 Technology24594—Rev.
3.13—July 2007LFENCELoad FenceActs as a barrier to force strong memory ordering (serialization) between load instructions precedingthe LFENCE and load instructions that follow the LFENCE. Loads from differing memory types maybe performed out of order, in particular between WC/WC+ and other memory types. The LFENCEinstruction assures that the system completes all previous loads before executing subsequent loads.The LFENCE instruction is weakly-ordered with respect to store instructions, data and instructionprefetches, and the SFENCE instruction.
Speculative loads initiated by the processor, or specifiedexplicitly using cache-prefetch instructions, can be reordered around an LFENCE.In addition to load instructions, the LFENCE instruction is strongly ordered with respect to otherLFENCE instructions, MFENCE instructions, and serializing instructions. Further details on the useof MFENCE to order accesses among differing memory types may be found in AMD64 ArchitectureProgrammer’s Manual Volume 2: System Programming, section 7.4 “Memory Types” on page 168.Support for the LFENCE instruction is indicated when the SSE2 bit (bit 26) is set to 1 in EDX afterexecuting CPUID function 0000_0001h.MnemonicOpcodeLFENCE0F AE E8DescriptionForce strong ordering of (serialize) load operations.Related InstructionsMFENCE, SFENCErFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UD148VirtualReal 8086 ProtectedXXXCause of ExceptionThe LFENCE instruction is not supported as indicated by EDXbit 26 of CPUID function 0000_0001h.LFENCEInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyLODSLODSBLODSWLODSDLODSQLoad StringCopies the byte, word, doubleword, or quadword in the memory location pointed to by the DS:rSIregisters to the AL, AX, EAX, or RAX register, depending on the size of the operand, and thenincrements or decrements the rSI register according to the state of the DF flag in the rFLAGS register.If the DF flag is 0, the instruction increments rSI; otherwise, it decrements rSI.
It increments ordecrements rSI by 1, 2, 4, or 8, depending on the number of bytes being loaded.The forms of the LODS instruction with an explicit operand address the operand at seg:[rSI]. Thevalue of seg defaults to the DS segment, but may be overridden by a segment prefix. The explicitoperand serves only to specify the type (size) of the value being copied and the specific registers used.The no-operands forms of the instruction always use the DS:[rSI] registers to point to the value to becopied (they do not allow a segment prefix).
The mnemonic determines the size of the operand and thespecific registers used.The LODSx instructions support the REP prefixes. For details about the REP prefixes, see “RepeatPrefixes” on page 9. More often, software uses the LODSx instruction inside a loop controlled by aLOOPcc instruction as a more efficient replacement for instructions like:mov eax, dword ptr ds:[esi]add esi, 4The LODSQ instruction can only be used in 64-bit mode.MnemonicOpcodeDescriptionLODS mem8ACLoad byte at DS:rSI into AL and then increment ordecrement rSI.LODS mem16ADLoad word at DS:rSI into AX and then increment ordecrement rSI.LODS mem32ADLoad doubleword at DS:rSI into EAX and thenincrement or decrement rSI.LODS mem64ADLoad quadword at DS:rSI into RAX and then incrementor decrement rSI.LODSBACLoad byte at DS:rSI into AL and then increment ordecrement rSI.LODSWADLoad the word at DS:rSI into AX and then increment ordecrement rSI.Instruction ReferenceLODSx149AMD64 Technology24594—Rev.
3.13—July 2007MnemonicOpcodeDescriptionLODSDADLoad doubleword at DS:rSI into EAX and thenincrement or decrement rSI.LODSQADLoad quadword at DS:rSI into RAX and then incrementor decrement rSI.Related InstructionsMOVSx, STOSxrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.150LODSxInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyLOOPLOOPELOOPNELOOPNZLOOPZLoopDecrements the count register (rCX) by 1, then, if rCX is not 0 and the ZF flag meets the conditionspecified by the mnemonic, it jumps to the target instruction specified by the signed 8-bit relativeoffset. Otherwise, it continues with the next instruction after the LOOPcc instruction.The size of the count register used (CX, ECX, or RCX) depends on the address-size attribute of theLOOPcc instruction.The LOOP instruction ignores the state of the ZF flag.The LOOPE and LOOPZ instructions jump if rCX is not 0 and the ZF flag is set to 1.
In other words,the instruction exits the loop (falls through to the next instruction) if rCX becomes 0 or ZF = 0.The LOOPNE and LOOPNZ instructions jump if rCX is not 0 and ZF flag is cleared to 0. In otherwords, the instruction exits the loop if rCX becomes 0 or ZF = 1.The LOOPcc instruction does not change the state of the ZF flag. Typically, the loop contains acompare instruction to set or clear the ZF flag.If the jump is taken, the signed displacement is added to the rIP (of the following instruction) and theresult is truncated to 16, 32, or 64 bits, depending on operand size.In 64-bit mode, the operand size defaults to 64 bits without the need for a REX prefix, and theprocessor sign-extends the 8-bit offset before adding it to the RIP.MnemonicOpcodeDescriptionLOOP rel8offE2 cbDecrement rCX, then jump short if rCX is not 0.LOOPE rel8offE1 cbDecrement rCX, then jump short if rCX is not 0 and ZFis 1.LOOPNE rel8offE0 cbDecrement rCX, then Jump short if rCX is not 0 and ZFis 0.LOOPNZ rel8offE0 cbDecrement rCX, then Jump short if rCX is not 0 and ZFis 0.LOOPZ rel8offE1 cbDecrement rCX, then Jump short if rCX is not 0 and ZFis 1.Related InstructionsNoneInstruction ReferenceLOOPcc151AMD64 Technology24594—Rev.
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