Volume 3 General-Purpose and System Instructions (794097), страница 33
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3.13—July 2007AMD64 TechnologyORLogical ORPerforms a logical OR on the bits in a register, memory location, or immediate value (second operand)and a register or memory location (first operand) and stores the result in the first operand location. Thetwo operands cannot both be memory locations.If both corresponding bits are 0, the corresponding bit of the result is 0; otherwise, the correspondingresult bit is 1.The forms of the OR instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionOR AL, imm80C ibOR the contents of AL with an immediate 8-bit value.OR AX, imm160D iwOR the contents of AX with an immediate 16-bit value.OR EAX, imm320D idOR the contents of EAX with an immediate 32-bit value.OR RAX, imm320D idOR the contents of RAX with a sign-extendedimmediate 32-bit value.OR reg/mem8, imm880 /1 ibOR the contents of an 8-bit register or memory operandand an immediate 8-bit value.OR reg/mem16, imm1681 /1 iwOR the contents of a 16-bit register or memory operandand an immediate 16-bit value.OR reg/mem32, imm3281 /1 idOR the contents of a 32-bit register or memory operandand an immediate 32-bit value.OR reg/mem64, imm3281 /1 idOR the contents of a 64-bit register or memory operandand sign-extended immediate 32-bit value.OR reg/mem16, imm883 /1 ibOR the contents of a 16-bit register or memory operandand a sign-extended immediate 8-bit value.OR reg/mem32, imm883 /1 ibOR the contents of a 32-bit register or memory operandand a sign-extended immediate 8-bit value.OR reg/mem64, imm883 /1 ibOR the contents of a 64-bit register or memory operandand a sign-extended immediate 8-bit value.OR reg/mem8, reg808 /rOR the contents of an 8-bit register or memory operandwith the contents of an 8-bit register.OR reg/mem16, reg1609 /rOR the contents of a 16-bit register or memory operandwith the contents of a 16-bit register.OR reg/mem32, reg3209 /rOR the contents of a 32-bit register or memory operandwith the contents of a 32-bit register.OR reg/mem64, reg6409 /rOR the contents of a 64-bit register or memory operandwith the contents of a 64-bit register.OR reg8, reg/mem80A /rOR the contents of an 8-bit register with the contents ofan 8-bit register or memory operand.Instruction ReferenceOR179AMD64 Technology24594—Rev.
3.13—July 2007MnemonicOpcodeDescriptionOR reg16, reg/mem160B /rOR the contents of a 16-bit register with the contents ofa 16-bit register or memory operand.OR reg32, reg/mem320B /rOR the contents of a 32-bit register with the contents ofa 32-bit register or memory operand.OR reg64, reg/mem640B /rOR the contents of a 64-bit register with the contents ofa 64-bit register or memory operand.The following chart summarizes the effect of this instruction:XYX OR Y000011101111Related InstructionsAND, NEG, NOT, XORrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTF02120191817161413–12111098SFZFAFPFCFMMUM076420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.180ORInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyOUTOutput to PortCopies the value from the AL, AX, or EAX register (second operand) to an I/O port (first operand).The port address can be a byte-immediate value (00h to FFh) or the value in the DX register (0000h toFFFFh). The source register used determines the size of the port (8, 16, or 32 bits).If the operand size is 64 bits, OUT only writes to a 32-bit I/O port.If the CPL is higher than the IOPL or the mode is virtual mode, OUT checks the I/O permission bitmapin the TSS before allowing access to the I/O port. See Volume 2 for details on the TSS I/O permissionbitmap.MnemonicOpcodeDescriptionOUT imm8, ALE6 ibOutput the byte in the AL register to the port specified byan 8-bit immediate value.OUT imm8, AXE7 ibOutput the word in the AX register to the port specifiedby an 8-bit immediate value.OUT imm8, EAXE7 ibOutput the doubleword in the EAX register to the portspecified by an 8-bit immediate value.OUT DX, ALEEOutput byte in AL to the output port specified in DX.OUT DX, AXEFOutput word in AX to the output port specified in DX.OUT DX, EAXEFOutput doubleword in EAX to the output port specified inDX.Related InstructionsIN, INSx, OUTSxrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedGeneral protection,#GPPage fault (#PF)Instruction ReferenceOne or more I/O permission bits were set in the TSS for theaccessed port.XXCause of ExceptionXThe CPL was greater than the IOPL and one or more I/Opermission bits were set in the TSS for the accessed port.XA page fault resulted from the execution of the instruction.OUT181AMD64 Technology24594—Rev.
3.13—July 2007OUTSOUTSBOUTSWOUTSDOutput StringCopies data from the memory location pointed to by DS:rSI to the I/O port address (0000h to FFFFh)specified in the DX register, and then increments or decrements the rSI register according to the settingof the DF flag in the rFLAGS register.If the DF flag is 0, the instruction increments rSI; otherwise, it decrements rSI.
It increments ordecrements the pointer by 1, 2, or 4, depending on the size of the value being copied.The OUTSx instruction uses an explicit memory operand (second operand) to determine the type (size)of the value being copied, but always uses DS:rSI for the location of the value to copy. The explicitregister operand specifies the I/O port address and must always be DX.The no-operands forms of the instruction use the DS:[rSI] register pair to point to the data to be copiedand the DX register as the destination. The mnemonic specifies the size of the I/O port and the type(size) of the value being copied.The OUTSx instruction supports the REP prefix. For details about the REP prefix, see “RepeatPrefixes” on page 9.If the operand size is 64-bits, OUTS only writes to a 32-bit I/O port.If the CPL is higher than the IOPL or the mode is virtual mode, OUTSx checks the I/O permissionbitmap in the TSS before allowing access to the I/O port.
See Volume 2 for details on the TSS I/Opermission bitmap.MnemonicOpcodeDescriptionOUTS DX, mem86EOutput the byte in DS:rSI to the port specified in DX,then increment or decrement rSI.OUTS DX, mem166FOutput the word in DS:rSI to the port specified in DX,then increment or decrement rSI.OUTS DX, mem326FOutput the doubleword in DS:rSI to the port specified inDX, then increment or decrement rSI.OUTSB6EOutput the byte in DS:rSI to the port specified in DX,then increment or decrement rSI.OUTSW6FOutput the word in DS:rSI to the port specified in DX,then increment or decrement rSI.OUTSD6FOutput the doubleword in DS:rSI to the port specified inDX, then increment or decrement rSI.182OUTSxInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyRelated InstructionsIN, INSx, OUTrFLAGS AffectedNoneExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.General protection,#GPOne or more I/O permission bits were set in the TSS for theaccessed port.XXThe CPL was greater than the IOPL and one or more I/Opermission bits were set in the TSS for the accessed port.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference is performed while alignmentchecking was enabled.Instruction ReferenceOUTSx183AMD64 Technology24594—Rev.
3.13—July 2007PAUSEPauseImproves the performance of spin loops, by providing a hint to the processor that the current code is ina spin loop. The processor may use this to optimize power consumption while in the spin loop.Architecturally, this instruction behaves like a NOP instruction.Processors that do not support PAUSE treat this opcode as a NOP instruction.MnemonicPAUSEOpcodeF3 90DescriptionProvides a hint to processor that a spin loop is beingexecuted.Related InstructionsNonerFLAGS AffectedNoneExceptionsNone184PAUSEInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyPOPPop StackCopies the value pointed to by the stack pointer (SS:rSP) to the specified register or memory locationand then increments the rSP by 2 for a 16-bit pop, 4 for a 32-bit pop, or 8 for a 64-bit pop.The operand-size attribute determines the amount by which the stack pointer is incremented (2, 4 or 8bytes). The stack-size attribute determines whether SP, ESP, or RSP is incremented.For forms of the instruction that load a segment register (POP DS, POP ES, POP FS, POP GS, POPSS), the source operand must be a valid segment selector. When a segment selector is popped into asegment register, the processor also loads all associated descriptor information into the hidden part ofthe register and validates it.It is possible to pop a null segment selector value (0000–0003h) into the DS, ES, FS, or GS register.This action does not cause a general protection fault, but a subsequent reference to such a segmentdoes cause a #GP exception.
For more information about segment selectors, see “Segment Selectorsand Registers” on page 67.In 64-bit mode, the POP operand size defaults to 64 bits and there is no prefix available to encode a 32bit operand size. Using POP DS, POP ES, or POP SS instruction in 64-bit mode generates an invalidopcode exception.This instruction cannot pop a value into the CS register. The RET (Far) instruction performs thisfunction.MnemonicOpcodeDescriptionPOP reg/mem168F /0Pop the top of the stack into a 16-bit register or memorylocation.POP reg/mem328F /0Pop the top of the stack into a 32-bit register or memorylocation.(No prefix for encoding this in 64-bit mode.)POP reg/mem648F /0Pop the top of the stack into a 64-bit register or memorylocation.POP reg1658 +rwPop the top of the stack into a 16-bit register.POP reg3258 +rdPop the top of the stack into a 32-bit register.(No prefix for encoding this in 64-bit mode.)POP reg6458 +rqPop the top of the stack into a 64-bit register.POP DS1FPop the top of the stack into the DS register.(Invalid in 64-bit mode.)POP ES07Pop the top of the stack into the ES register.(Invalid in 64-bit mode.)POP SS17Pop the top of the stack into the SS register.(Invalid in 64-bit mode.)Instruction ReferencePOP185AMD64 Technology24594—Rev.
3.13—July 2007MnemonicOpcodeDescriptionPOP FS0F A1Pop the top of the stack into the FS register.POP GS0F A9Pop the top of the stack into the GS register.Related InstructionsPUSHrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionInvalid opcode, #UDXPOP DS, POP ES, or POP SS was executed in 64-bit mode.Segment notpresent, #NP(selector)XThe DS, ES, FS, or GS register was loaded with a non-nullsegment selector and the segment was marked not present.XA memory address exceeded the stack segment limit or wasnon-canonical.XThe SS register was loaded with a non-null segment selectorand the segment was marked not present.XA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.XA segment register was loaded and the segment descriptorexceeded the descriptor table limit.XA segment register was loaded and the segment selector’s TIbit was set, but the LDT selector was a null selector.XThe SS register was loaded with a null segment selector innon-64-bit mode or while CPL = 3.XThe SS register was loaded and the segment selector RPLand the segment descriptor DPL were not equal to the CPL.XThe SS register was loaded and the segment pointed to wasnot a writable data segment.XThe DS, ES, FS, or GS register was loaded and the segmentpointed to was a data or non-conforming code segment, butthe RPL or the CPL was greater than the DPL.XThe DS, ES, FS, or GS register was loaded and the segmentpointed to was not a data segment or readable code segment.Stack, #SSXXStack, #SS(selector)XXGeneral protection,#GPGeneral protection,#GP(selector)Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.186POPInstruction Reference24594—Rev.
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