Volume 3 General-Purpose and System Instructions (794097), страница 36
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When the rotate count is greater than 1, the OF flag is undefined.When the rotate count is 0, no flags are affected.MnemonicOpcodeDescriptionRCL reg/mem8,1D0 /2Rotate the 9 bits consisting of the carry flag and an 8-bitregister or memory location left 1 bit.RCL reg/mem8, CLD2 /2Rotate the 9 bits consisting of the carry flag and an 8-bitregister or memory location left the number of bitsspecified in the CL register.RCL reg/mem8, imm8C0 /2 ibRotate the 9 bits consisting of the carry flag and an 8-bitregister or memory location left the number of bitsspecified by an 8-bit immediate value.RCL reg/mem16, 1D1 /2Rotate the 17 bits consisting of the carry flag and a 16bit register or memory location left 1 bit.RCL reg/mem16, CLD3 /2Rotate the 17 bits consisting of the carry flag and a 16bit register or memory location left the number of bitsspecified in the CL register.RCL reg/mem16, imm8C1 /2 ibRotate the 17 bits consisting of the carry flag and a 16bit register or memory location left the number of bitsspecified by an 8-bit immediate value.RCL reg/mem32, 1D1 /2Rotate the 33 bits consisting of the carry flag and a 32bit register or memory location left 1 bit.RCL reg/mem32, CLD3 /2Rotate 33 bits consisting of the carry flag and a 32-bitregister or memory location left the number of bitsspecified in the CL register.RCL reg/mem32, imm8C1 /2 ibRotate the 33 bits consisting of the carry flag and a 32bit register or memory location left the number of bitsspecified by an 8-bit immediate value.RCL reg/mem64, 1D1 /2Rotate the 65 bits consisting of the carry flag and a 64bit register or memory location left 1 bit.202RCLInstruction Reference24594—Rev.
3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionRCL reg/mem64, CLD3 /2Rotate the 65 bits consisting of the carry flag and a 64bit register or memory location left the number of bitsspecified in the CL register.RCL reg/mem64, imm8C1 /2 ibRotates the 65 bits consisting of the carry flag and a 64bit register or memory location left the number of bitsspecified by an 8-bit immediate value.Related InstructionsRCR, ROL, RORrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFM2120191817161413–1211CFM109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceRCL203AMD64 Technology24594—Rev. 3.13—July 2007RCRRotate Through Carry RightRotates the bits of a register or memory location (first operand) to the right (toward the less significantbit positions) and through the carry flag by the number of bit positions in an unsigned immediate valueor the CL register (second operand).
The bits rotated through the carry flag are rotated back in at theleft end (msb) of the first operand location.The processor masks the upper three bits in the count operand, thus restricting the count to a numberbetween 0 and 31. When the destination is 64 bits wide, the processor masks the upper two bits of thecount, providing a count in the range of 0 to 63.For 1-bit rotates, the instruction sets the OF flag to the exclusive OR of the CF flag (before the rotate)and the most significant bit of the original value.
When the rotate count is greater than 1, the OF flag isundefined. When the rotate count is 0, no flags are affected.MnemonicOpcodeDescriptionRCR reg/mem8, 1D0 /3Rotate the 9 bits consisting of the carry flag and an 8-bitregister or memory location right 1 bit.RCR reg/mem8,CLD2 /3Rotate the 9 bits consisting of the carry flag and an 8-bitregister or memory location right the number of bitsspecified in the CL register.RCR reg/mem8,imm8C0 /3 ibRotate the 9 bits consisting of the carry flag and an 8-bitregister or memory location right the number of bitsspecified by an 8-bit immediate value.RCR reg/mem16,1D1 /3Rotate the 17 bits consisting of the carry flag and a 16bit register or memory location right 1 bit.RCR reg/mem16,CLD3 /3Rotate the17 bits consisting of the carry flag and a 16bit register or memory location right the number of bitsspecified in the CL register.RCR reg/mem16, imm8C1 /3 ibRotate the 17 bits consisting of the carry flag and a 16bit register or memory location right the number of bitsspecified by an 8-bit immediate value.RCR reg/mem32,1D1 /3Rotate the 33 bits consisting of the carry flag and a 32bit register or memory location right 1 bit.RCR reg/mem32,CLD3 /3Rotate 33 bits consisting of the carry flag and a 32-bitregister or memory location right the number of bitsspecified in the CL register.RCR reg/mem32, imm8C1 /3 ibRotate the 33 bits consisting of the carry flag and a 32bit register or memory location right the number of bitsspecified by an 8-bit immediate value.RCR reg/mem64,1D1 /3Rotate the 65 bits consisting of the carry flag and a 64bit register or memory location right 1 bit.204RCRInstruction Reference24594—Rev.
3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionRCR reg/mem64,CLD3 /3Rotate 65 bits consisting of the carry flag and a 64-bitregister or memory location right the number of bitsspecified in the CL register.RCR reg/mem64, imm8C1 /3 ibRotate the 65 bits consisting of the carry flag and a 64bit register or memory location right the number of bitsspecified by an 8-bit immediate value.Related InstructionsRCL, ROR, ROLrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFM2120191817161413–1211CFM109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceRCR205AMD64 Technology24594—Rev. 3.13—July 2007RET (Near)Near Return from Called ProcedureReturns from a procedure previously entered by a CALL near instruction.
This form of the RETinstruction returns to a calling procedure within the current code segment.This instruction pops the rIP from the stack, with the size of the pop determined by the operand size.The new rIP is then zero-extended to 64 bits. The RET instruction can accept an immediate valueoperand that it adds to the rSP after it pops the target rIP. This action skips over any parameterspreviously passed back to the subroutine that are no longer needed.In 64-bit mode, the operand size defaults to 64 bits (eight bytes) without the need for a REX prefix. Noprefix is available to encode a 32-bit operand size in 64-bit mode.See RET (Far) for information on far returns—returns to procedures located outside of the currentcode segment. For details about control-flow instructions, see “Control Transfers” in Volume 1, and“Control-Transfer Privilege Checks” in Volume 2.MnemonicOpcodeDescriptionRETC3Near return to the calling procedure.RET imm16C2 iwNear return to the calling procedure then pop thespecified number of bytes from the stack.Related InstructionsCALL (Near), CALL (Far), RET (Far)rFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXThe target offset exceeded the code segment limit or was noncanonical.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.206RET (Near)Instruction Reference24594—Rev.
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