Volume 3 General-Purpose and System Instructions (794097), страница 31
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3.13—July 2007Related InstructionsMOV(CRn), MOV(DRn), MOVD, MOVSX, MOVZX, MOVSXD, MOVSxrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXSegment notpresent, #NP(selector)Stack, #SSXXStack, #SS(selector)XXGeneral protection,#GPGeneral protection,#GP(selector)Cause of ExceptionXAn attempt was made to load the CS register.XThe DS, ES, FS, or GS register was loaded with a non-nullsegment selector and the segment was marked not present.XA memory address exceeded the stack segment limit or wasnon-canonical.XThe SS register was loaded with a non-null segment selector,and the segment was marked not present.XA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.XA segment register was loaded, but the segment descriptorexceeded the descriptor table limit.XA segment register was loaded and the segment selector’s TIbit was set, but the LDT selector was a null selector.XThe SS register was loaded with a null segment selector innon-64-bit mode or while CPL = 3.XThe SS register was loaded and the segment selector RPLand the segment descriptor DPL were not equal to the CPL.XThe SS register was loaded and the segment pointed to wasnot a writable data segment.XThe DS, ES, FS, or GS register was loaded and the segmentpointed to was a data or non-conforming code segment, butthe RPL or CPL was greater than the DPL.XThe DS, ES, FS, or GS register was loaded and the segmentpointed to was not a data segment or readable code segment.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.158MOVInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyMOVDMove Doubleword or QuadwordMoves a 32-bit or 64-bit value in one of the following ways:••••from a 32-bit or 64-bit general-purpose register or memory location to the low-order 32 or 64 bitsof an XMM register, with zero-extension to 128 bitsfrom the low-order 32 or 64 bits of an XMM to a 32-bit or 64-bit general-purpose register ormemory locationfrom a 32-bit or 64-bit general-purpose register or memory location to the low-order 32 bits (withzero-extension to 64 bits) or the full 64 bits of an MMX registerfrom the low-order 32 or the full 64 bits of an MMX register to a 32-bit or 64-bit general-purposeregister or memory locationMnemonicOpcodeDescriptionMOVD xmm, reg/mem3266 0F 6E /rMove 32-bit value from a general-purpose register or32-bit memory location to an XMM register.MOVD xmm, reg/mem6466 0F 6E /rMove 64-bit value from a general-purpose register or64-bit memory location to an XMM register.MOVD reg/mem32, xmm66 0F 7E /rMove 32-bit value from an XMM register to a 32-bitgeneral-purpose register or memory location.MOVD reg/mem64, xmm66 0F 7E /rMove 64-bit value from an XMM register to a 64-bitgeneral-purpose register or memory location.MOVD mmx, reg/mem320F 6E /rMove 32-bit value from a general-purpose register or32-bit memory location to an MMX register.MOVD mmx, reg/mem640F 6E /rMove 64-bit value from a general-purpose register or64-bit memory location to an MMX register.MOVD reg/mem32, mmx0F 7E /rMove 32-bit value from an MMX register to a 32-bitgeneral-purpose register or memory location.MOVD reg/mem64, mmx0F 7E /rMove 64-bit value from an MMX register to a 64-bitgeneral-purpose register or memory location.The diagrams in Figure 3-1 on page 160 illustrate the operation of the MOVD instruction.Instruction ReferenceMOVD159AMD64 Technology24594—Rev.
3.13—July 2007xmmreg/mem3212732 3131000xmm127reg/mem6464 6363000with REX prefixreg/mem32All operationsare "copy"310xmm12732 31reg/mem64630xmm012764 630with REX prefixmmx6332 31reg/mem3231000mmx63reg/mem640630with REX prefixreg/mem3231mmx063reg/mem646332 310mmx063with REX prefix0movd.epsFigure 3-1. MOVD Instruction Operation160MOVDInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyRelated InstructionsMOVDQA, MOVDQU, MOVDQ2Q, MOVQ, MOVQ2DQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptions (All Modes)RealVirtual8086ProtectedDescriptionXXXThe MMX instructions are not supported, as indicatedby EDX bit 23 of CPUID function 0000_0001h.XXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe instruction used XMM registers whileCR4.OSFXSR=0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XXA page fault resulted from the execution of theinstruction.XXAn x87 floating-point exception was pending and theinstruction referenced an MMX register.XXAn unaligned memory reference was performed whilealignment checking was enabled.ExceptionInvalid opcode, #UDPage fault, #PFx87 floating-pointexception pending,#MFAlignment check, #ACInstruction ReferenceXMOVD161AMD64 Technology24594—Rev.
3.13—July 2007MOVMSKPDExtract Packed Double-PrecisionFloating-Point Sign MaskMoves the sign bits of two packed double-precision floating-point values in an XMM register (secondoperand) to the two low-order bits of a general-purpose register (first operand) with zero-extension.The MOVMSKPD instruction is an SSE2 instruction; Check the status of EDX bit 26 of CPUIDfunction 0000_0001h to verify that the processor supports this function.MnemonicOpcodeMOVMSKPD reg32, xmmDescriptionMove sign bits 127 and 63 in an XMM register to a 32-bitgeneral-purpose register.66 0F 50 /rreg32xmm13101276300copy signcopy signmovmskpd.epsRelated InstructionsMOVMSKPS, PMOVMSKBrFLAGS AffectedNoneMXCSR Flags AffectedNone162MOVMSKPDInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyExceptionsException (vector)Invalid opcode, #UDDevice not available,#NMInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe task-switch bit (TS) of CR0 was set to 1.MOVMSKPD163AMD64 Technology24594—Rev. 3.13—July 2007MOVMSKPSExtract Packed Single-PrecisionFloating-Point Sign MaskMoves the sign bits of four packed single-precision floating-point values in an XMM register (secondoperand) to the four low-order bits of a general-purpose register (first operand) with zero-extension.The MOVMSKPD instruction is an SSE2 instruction; Check the status of EDX bit 26 of CPUIDfunction 0000_0001h to verify that the processor supports this function.MnemonicOpcodeMOVMSKPS reg32, xmmDescriptionMove sign bits 127, 95, 63, 31 in an XMM register to a32-bit general-purpose register.0F 50 /rreg32xmm3310127956331copy signcopy signcopy signcopy sign00movmskps.epsRelated InstructionsMOVMSKPD, PMOVMSKBrFLAGS AffectedNoneMXCSR Flags AffectedNone164MOVMSKPSInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyExceptionsExceptionInvalid opcode, #UDDevice not available,#NMInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe task-switch bit (TS) of CR0 was set to 1.MOVMSKPS165AMD64 Technology24594—Rev. 3.13—July 2007MOVNTIMove Non-Temporal Doubleword orQuadwordStores a value in a 32-bit or 64-bit general-purpose register (second operand) in a memory location(first operand).
This instruction indicates to the processor that the data is non-temporal and is unlikelyto be used again soon. The processor treats the store as a write-combining (WC) memory write, whichminimizes cache pollution. The exact method by which cache pollution is minimized depends on thehardware implementation of the instruction. For further information, see “Memory Optimization” inVolume 1.The MOVNTI instruction is weakly-ordered with respect to other instructions that operate on memory.Software should use an SFENCE instruction to force strong memory ordering of MOVNTI withrespect to other stores.Support for the MOVNTI instruction is indicated when the SSE2 bit (bit 26) is set to 1 in EDX afterexecuting CPUID function 0000_0001h.MnemonicOpcodeDescriptionMOVNTI mem32, reg320F C3 /rStores a 32-bit general-purpose register value into a 32bit memory location, minimizing cache pollution.MOVNTI mem64, reg640F C3 /rStores a 64-bit general-purpose register value into a 64bit memory location, minimizing cache pollution.Related InstructionsMOVNTDQ, MOVNTPD, MOVNTPS, MOVNTQrFLAGS AffectedNoneExceptionsException (vector)RealVirtual8086 ProtectedCause of ExceptionInvalid opcode, #UDXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.General protection,#GP166MOVNTIInstruction Reference24594—Rev.
3.13—July 2007Exception (vector)RealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVNTI167AMD64 Technology24594—Rev.
3.13—July 2007MOVSMOVSBMOVSWMOVSDMOVSQMove StringMoves a byte, word, doubleword, or quadword from the memory location pointed to by DS:rSI to thememory location pointed to by ES:rDI, and then increments or decrements the rSI and rDI registersaccording to the state of the DF flag in the rFLAGS register.If the DF flag is 0, the instruction increments both pointers; otherwise, it decrements them.
Itincrements or decrements the pointers by 1, 2, 4, or 8, depending on the size of the operands.The forms of the MOVSx instruction with explicit operands address the first operand at seg:[rSI]. Thevalue of seg defaults to the DS segment, but can be overridden by a segment prefix. These instructionsalways address the second operand at ES:[rDI] (ES may not be overridden). The explicit operandsserve only to specify the type (size) of the value being moved.The no-operands forms of the instruction use the DS:[rSI] and ES:[rDI] registers to point to the valueto be moved (they do not allow a segment prefix). The mnemonic determines the size of the operands.Do not confuse this MOVSD instruction with the same-mnemonic MOVSD (move scalar doubleprecision floating-point) instruction in the 128-bit media instruction set.
Assemblers can distinguishthe instructions by the number and type of operands.The MOVSx instructions support the REP prefixes. For details about the REP prefixes, see “RepeatPrefixes” on page 9.MnemonicOpcodeDescriptionMOVS mem8, mem8A4Move byte at DS:rSI to ES:rDI, and then increment ordecrement rSI and rDI.MOVS mem16, mem16A5Move word at DS:rSI to ES:rDI, and then increment ordecrement rSI and rDI.MOVS mem32, mem32A5Move doubleword at DS:rSI to ES:rDI, and thenincrement or decrement rSI and rDI.MOVS mem64, mem64A5Move quadword at DS:rSI to ES:rDI, and then incrementor decrement rSI and rDI.MOVSBA4Move byte at DS:rSI to ES:rDI, and then increment ordecrement rSI and rDI.MOVSWA5Move word at DS:rSI to ES:rDI, and then increment ordecrement rSI and rDI.168MOVSxInstruction Reference24594—Rev.
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