Volume 3 General-Purpose and System Instructions (794097), страница 28
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Additionally, the targetselector can also be a call gate in protected mode, or a task gate or TSS selector in legacy protectedmode.•••Target is a code segment—Control is transferred to the target CS:rIP. In this case, the target offsetcan only be a 16 or 32 bit value, depending on operand-size, and is zero-extended to 64 bits. NoCPL change is allowed.Target is a call gate—The call gate specifies the actual target code segment and offset, and controlis transferred to the target CS:rIP. When jumping through a call gate, the size of the target rIP is 16,32, or 64 bits, depending on the size of the call gate. If the target rIP is less than 64 bits, it's zeroextended to 64 bits.
In long mode, only 64-bit call gates are allowed, and they must point to 64-bitcode segments. No CPL change is allowed.Target is a task gate or a TSS—If the mode is legacy protected mode, then a task switch occurs. See“Hardware Task-Management in Legacy Mode” in volume 2 for details about task switches.Hardware task switches are not supported in long mode.See JMP (Near) for information on near jumps—jumps to procedures located inside the current codesegment. For details about control-flow instructions, see “Control Transfers” in Volume 1, and“Control-Transfer Privilege Checks” in Volume 2.MnemonicOpcodeDescriptionJMP FAR pntr16:16EA cdFar jump direct, with the target specified by a far pointercontained in the instruction. (Invalid in 64-bit mode.)JMP FAR pntr16:32EA cpFar jump direct, with the target specified by a far pointercontained in the instruction.
(Invalid in 64-bit mode.)JMP FAR mem16:16FF /5Far jump indirect, with the target specified by a farpointer in memory.JMP FAR mem16:32FF /5Far jump indirect, with the target specified by a farpointer in memory.Instruction ReferenceJMP (Far)137AMD64 Technology24594—Rev. 3.13—July 2007Action// Far jumps (JMPF)// See “Pseudocode Definitions” on page 41.JMPF_START:IF (REAL_MODE)JMPF_REAL_OR_VIRTUALELSIF (PROTECTED_MODE)JMPF_PROTECTEDELSE // (VIRTUAL_MODE)JMPF_REAL_OR_VIRTUALJMPF_REAL_OR_VIRTUAL:IF (OPCODE = jmpf [mem]) //JMPF Indirect{temp_RIP = READ_MEM.z [mem]temp_CS = READ_MEM.w [mem+Z]}ELSE // (OPCODE = jmpf direct){temp_RIP = z-sized offset specified in the instruction,zero-extended to 64 bitstemp_CS = selector specified in the instruction}IF (temp_RIP>CS.limit)EXCEPTION [#GP(0)]CS.sel = temp_CSCS.base = temp_CS SHL 4RIP = temp_RIPEXITJMPF_PROTECTED:IF (OPCODE = jmpf [mem]) // JMPF Indirect{temp_offset = READ_MEM.z [mem]temp_sel= READ_MEM.w [mem+Z]}ELSE // (OPCODE = jmpf direct){IF (64BIT_MODE)EXCEPTION [#UD]// ’jmpf direct’ is illegal in 64-bit modetemp_offset = z-sized offset specified in the instruction,zero-extended to 64 bitstemp_sel= selector specified in the instruction}138JMP (Far)Instruction Reference24594—Rev.
3.13—July 2007AMD64 Technologytemp_desc = READ_DESCRIPTOR (temp_sel, cs_chk)// read descriptor, perform protection and type checksIF (temp_desc.attr.type = ’available_tss’)TASK_SWITCH// using temp_sel as the target tss selectorELSIF (temp_desc.attr.type = ’taskgate’)TASK_SWITCH// using the tss selector in the task gate as the// target tssELSIF (temp_desc.attr.type = ’code’)// if the selector refers to a code descriptor, then// the offset we read is the target RIP{temp_RIP = temp_offsetCS = temp_descIF ((!64BIT_MODE) && (temp_RIP > CS.limit))// temp_RIP can’t be non-canonical because// it’s a 16- or 32-bit offset, zero-extended to 64 bits{EXCEPTION [#GP(0)]}RIP = temp_RIPEXIT}ELSE{// (temp_desc.attr.type = ’callgate’)// if the selector refers to a call gate, then// the target CS and RIP both come from the call gatetemp_RIP = temp_desc.offsetIF (LONG_MODE){// in long mode, we need to read the 2nd half of a 16-byte call-gate// from the gdt/ldt to get the upper 32 bits of the target RIPtemp_upper = READ_MEM.q [temp_sel+8]IF (temp_upper’s extended attribute bits != 0)EXCEPTION [#GP(temp_sel)]// Make sure the extended// attribute bits are all zero.temp_RIP = tempRIP + (temp_upper SHL 32)// concatenate both halves of RIP}CS = READ_DESCRIPTOR (temp_desc.segment, clg_chk)// set up new CS base, attr, limitsIF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit))EXCEPTION [#GP(0)]RIP = temp_RIPEXIT}Instruction ReferenceJMP (Far)139AMD64 Technology24594—Rev.
3.13—July 2007Related InstructionsJMP (Near), Jcc, JrCXrFLAGS AffectedNone, unless a task switch occurs, in which case all flags are modified.ExceptionsExceptionVirtualReal 8086 ProtectedXXInvalid opcode, #UDSegment notpresent, #NP(selector)Stack, #SSGeneral protection,#GP140Cause of ExceptionXThe far JUMP indirect opcode (FF /5) had a register operand.XThe far JUMP direct opcode (EA) was executed in 64-bitmode.XThe accessed code segment, call gate, task gate, or TSS wasnot present.XXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XXXThe target offset exceeded the code segment limit or was noncanonical.XA null data segment was used to reference memory.JMP (Far)Instruction Reference24594—Rev. 3.13—July 2007ExceptionAMD64 TechnologyVirtualReal 8086 ProtectedGeneral protection,#GP(selector)Cause of ExceptionXThe target code segment selector was a null selector.XA code, call gate, task gate, or TSS descriptor exceeded thedescriptor table limit.XA segment selector’s TI bit was set, but the LDT selector wasa null selector.XThe segment descriptor specified by the instruction was not acode segment, task gate, call gate or available TSS in legacymode, or not a 64-bit code segment or a 64-bit call gate in longmode.XThe RPL of the non-conforming code segment selectorspecified by the instruction was greater than the CPL, or itsDPL was not equal to the CPL.XThe DPL of the conforming code segment descriptor specifiedby the instruction was greater than the CPL.XThe DPL of the callgate, taskgate, or TSS descriptor specifiedby the instruction was less than the CPL or less than its ownRPL.XThe segment selector specified by the call gate or task gatewas a null selector.XThe segment descriptor specified by the call gate was not acode segment in legacy mode or not a 64-bit code segment inlong mode.XThe DPL of the segment descriptor specified the call gate wasgreater than the CPL and it is a conforming segment.XThe DPL of the segment descriptor specified by the callgatewas not equal to the CPL and it is a non-conforming segment.XThe 64-bit call gate’s extended attribute bits were not zero.XThe TSS descriptor was found in the LDT.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceJMP (Far)141AMD64 Technology24594—Rev.
3.13—July 2007LAHFLoad Status Flags into AH RegisterLoads the lower 8 bits of the rFLAGS register, including sign flag (SF), zero flag (ZF), auxiliary carryflag (AF), parity flag (PF), and carry flag (CF), into the AH register.The instruction sets the reserved bits 1, 3, and 5 of the rFLAGS register to 1, 0, and 0, respectively, inthe AH register.The LAHF instruction can only be executed in 64-bit mode if supported by the processorimplementation. Check the status of ECX bit 0 returned by CPUID function 8000_0001h to verify thatthe processor supports LAHF in 64-bit mode.MnemonicOpcodeLAHFDescriptionLoad the SF, ZF, AF, PF, and CF flags into the AHregister.9FRelated InstructionsSAHFrFLAGS AffectedNone.ExceptionsExceptionInvalid opcode, #UD142VirtualReal 8086 ProtectedXCause of ExceptionThis instruction is not supported in 64-bit mode, as indicatedby ECX bit 0 returned by CPUID function 8000_0001h.LAHFInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyLDSLESLFSLGSLSSLoad Far PointerLoads a far pointer from a memory location (second operand) into a segment register (mnemonic) andgeneral-purpose register (first operand). The instruction stores the 16-bit segment selector of thepointer into the segment register and the 16-bit or 32-bit offset portion into the general-purposeregister. The operand-size attribute determines whether the pointer is 32-bit or 48-bit.These instructions load associated segment-descriptor information into the hidden portion of thespecified segment register.Using LDS or LES in 64-bit mode generates an invalid-opcode exception.Executing LFS, LGS, or LSS with a 64-bit operand size only loads a 32-bit general purpose registerand the specified segment register.MnemonicOpcodeDescriptionLDS reg16, mem16:16C5 /rLoad DS:reg16 with a far pointer from memory.(Invalid in 64-bit mode.)LDS reg32, mem16:32C5 /rLoad DS:reg32 with a far pointer from memory.(Invalid in 64-bit mode.)LES reg16, mem16:16C4 /rLoad ES:reg16 with a far pointer from memory.(Invalid in 64-bit mode.)LES reg32, mem16:32C4 /rLoad ES:reg32 with a far pointer from memory.(Invalid in 64-bit mode.)LFS reg16, mem16:160F B4 /rLoad FS:reg16 with a far pointer from memory.LFS reg32, mem16:320F B4 /rLoad FS:reg32 with a far pointer from memory.LGS reg16, mem16:160F B5 /rLoad GS:reg16 with a far pointer from memory.LGS reg32, mem16:320F B5 /rLoad GS:reg32 with a far pointer from memory.LSS reg16, mem16:160F B2 /rLoad SS:reg16 with a far pointer from memory.LSS reg32, mem16:320F B2 /rLoad SS:reg32 with a far pointer from memory.Related InstructionsNonerFLAGS AffectedNoneInstruction ReferenceLxS143AMD64 Technology24594—Rev.
3.13—July 2007ExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXSegment notpresent, #NP(selector)Stack, #SSXXStack, #SS(selector)General protection,#GPXXGeneral protection,#GP(selector)Cause of ExceptionXThe source operand was a register.XLDS or LES was executed in 64-bit mode.XThe DS, ES, FS, or GS register was loaded with a non-nullsegment selector and the segment was marked not present.XA memory address exceeded the stack segment limit or wasnon-canonical.XThe SS register was loaded with a non-null segment selectorand the segment was marked not present.XA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.XA segment register was loaded, but the segment descriptorexceeded the descriptor table limit.XA segment register was loaded and the segment selector’s TIbit was set, but the LDT selector was a null selector.XThe SS register was loaded with a null segment selector innon-64-bit mode or while CPL = 3.XThe SS register was loaded and the segment selector RPLand the segment descriptor DPL were not equal to the CPL.XThe SS register was loaded and the segment pointed to wasnot a writable data segment.XThe DS, ES, FS, or GS register was loaded and the segmentpointed to was a data or non-conforming code segment, butthe RPL or CPL was greater than the DPL.XThe DS, ES, FS, or GS register was loaded and the segmentpointed to was not a data segment or readable code segment.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.144LxSInstruction Reference24594—Rev.
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