Volume 3 General-Purpose and System Instructions (794097), страница 23
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Otherwise,copy the memory location to EDX:EAX and clear thezero flag.0F C7 /1m128Compare RDX:RAX register to 128-bit memory location.If equal, set the zero flag (ZF) to 1 and copy theRCX:RBX register to the memory location. Otherwise,copy the memory location to RDX:RAX and clear thezero flag.Related InstructionsCMPXCHGInstruction ReferenceCMPXCHG8/16B101AMD64 Technology24594—Rev. 3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF420M2120191817161413–1211109876Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedXXXThe CMPXCHG8B instruction is not supported, as indicatedby EDX bit 8 of CPUID function 0000_0001h or function8000_0001h.XThe CMPXCHG16B instruction is not supported, as indicatedby ECX bit 13 of CPUID function 0000_0001h.Invalid opcode, #UDStack, #SSCause of ExceptionXXXThe operand was a register.XXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.XThe memory operand for CMPXCHG16B was not aligned on a16-byte boundary.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.102CMPXCHG8/16BInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyCPUIDProcessor IdentificationProvides information about the processor and its capabilities through a number of different functions.Software should load the number of the CPUID function to execute into the EAX register beforeexecuting the CPUID instruction. The processor returns information in the EAX, EBX, ECX, andEDX registers; the contents and format of these registers depend on the function.The architecture supports CPUID information about standard functions and extended functions. Thestandard functions have numbers in the 0000_xxxxh series (for example, standard function 1). Todetermine the largest standard function number that a processor supports, execute CPUID function 0.The extended functions have numbers in the 8000_xxxxh series (for example, extendedfunction 8000_0001h).
To determine the largest extended function number that a processor supports,execute CPUID extended function 8000_0000h. If the value returned in EAX is greater than8000_0000h, the processor supports extended functions.Software operating at any privilege level can execute the CPUID instruction to collect this information.In 64-bit mode, this instruction works the same as in legacy mode except that it zero-extends 32-bitregister results to 64 bits.CPUID is a serializing instruction.MnemonicOpcodeCPUID0F A2DescriptionReturns information about the processor and itscapabilities. EAX specifies the function number, and thedata is returned in EAX, EBX, ECX, EDX.Testing for the CPUID InstructionTo avoid an invalid-opcode exception (#UD) on those processor implementations that do not supportthe CPUID instruction, software must first test to determine if the CPUID instruction is supported.Support for the CPUID instruction is indicated by the ability to write the ID bit in the rFLAGS register.Normally, 32-bit software uses the PUSHFD and POPFD instructions in an attempt to writerFLAGS.ID.
After reading the updated rFLAGS.ID bit, a comparison determines if the operationchanged its value. If the value changed, the processor executing the code supports the CPUIDinstruction. If the value did not change, rFLAGS.ID is not writable, and the processor does not supportthe CPUID instruction.The following code sample shows how to test for the presence of the CPUID instruction using 32-bitcode.pushfdpopmovxorpushpopfdeaxebx, eaxeax, 00200000heaxInstruction Reference;;;;;;save EFLAGSstore EFLAGS in EAXsave in EBX for later testingtoggle bit 21push to stacksave changed EAX to EFLAGSCPUID103AMD64 Technologypushfdpopcmpjzeaxeax, ebxNO_CPUID24594—Rev. 3.13—July 2007;;;;push EFLAGS to TOSstore EFLAGS in EAXsee if bit 21 has changedif no change, no CPUIDStandard Function 0 and Extended Function 8000_0000hCPUID standard function 0 loads the EAX register with the largest CPUID standard function numbersupported by the processor implementation; similarly, CPUID extended function 8000_0000h loadsthe EAX register with the largest extended function number supported.Standard function 0 and extended function 8000_0000h both load a 12-character string into the EBX,EDX, and ECX registers identifying the processor vendor.
For AMD processors, the string isAuthenticAMD. This string informs software that it should follow the AMD CPUID definition forsubsequent CPUID function calls. If the function returns another vendor’s string, software must usethat vendor’s CPUID definition when interpreting the results of subsequent CPUID function calls.Table 3-2 shows the contents of the EBX, EDX, and ECX registers after executing function 0 on anAMD processor.Table 3-2. Processor Vendor Return ValuesRegisterReturn ValueASCII CharactersEBX6874_7541h“h t u A”EDX6974_6E65h“i t n e”ECX444D_4163h“D M A c”For more detailed on CPUID standard and extended functions, see the AMD CPUID Specification,order# 25481.Related InstructionsNonerFLAGS AffectedNoneExceptionsNone104CPUIDInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyDAADecimal Adjust after AdditionAdjusts the value in the AL register into a packed BCD result and sets the CF and AF flags in therFLAGS register to indicate a decimal carry out of either nibble of AL.Use this instruction to adjust the result of a byte ADD instruction that performed the binary addition ofone 2-digit packed BCD values to another.The instruction performs the adjustment by adding 06h to AL if the lower nibble is greater than 9 or ifAF = 1.
Then 60h is added to AL if the original AL was greater than 99h or if CF = 1.If the lower nibble of AL was adjusted, the AF flag is set to 1. Otherwise AF is not modified. If theupper nibble of AL was adjusted, the CF flag is set to 1. Otherwise, CF is not modified. SF, ZF, and PFare set according to the final value of AL.Using this instruction in 64-bit mode generates an invalid-opcode (#UD) exception.MnemonicOpcodeDAADescriptionDecimal adjust AL.(Invalid in 64-bit mode.)27rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode, #UDInstruction ReferenceXCause of ExceptionThis instruction was executed in 64-bit mode.DAA105AMD64 Technology24594—Rev. 3.13—July 2007DASDecimal Adjust after SubtractionAdjusts the value in the AL register into a packed BCD result and sets the CF and AF flags in therFLAGS register to indicate a decimal borrow.Use this instruction to adjust the result of a byte SUB instruction that performed a binary subtraction ofone 2-digit, packed BCD value from another.This instruction performs the adjustment by subtracting 06h from AL if the lower nibble is greater than9 or if AF = 1. Then 60h is subtracted from AL if the original AL was greater than 99h or if CF = 1.If the adjustment changes the lower nibble of AL, the AF flag is set to 1; otherwise AF is not modified.If the adjustment results in a borrow for either nibble of AL, the CF flag is set to 1; otherwise CF is notmodified.
The SF, ZF, and PF flags are set according to the final value of AL.Using this instruction in 64-bit mode generates an invalid-opcode (#UD) exception.MnemonicOpcodeDASDescriptionDecimal adjusts AL after subtraction.(Invalid in 64-bit mode.)2FRelated InstructionsDAArFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionInvalid opcode, #UD106VirtualReal 8086 ProtectedXCause of ExceptionThis instruction was executed in 64-bit mode.DASInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyDECDecrement by 1Subtracts 1 from the specified register or memory location. The CF flag is not affected.The one-byte forms of this instruction (opcodes 48 through 4F) are used as REX prefixes in 64-bitmode.
See “REX Prefixes” on page 11.The forms of the DEC instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediateoperand of 1.MnemonicOpcodeDescriptionDEC reg/mem8FE /1Decrement the contents of an 8-bit register or memorylocation by 1.DEC reg/mem16FF /1Decrement the contents of a 16-bit register or memorylocation by 1.DEC reg/mem32FF /1Decrement the contents of a 32-bit register or memorylocation by 1.DEC reg/mem64FF /1Decrement the contents of a 64-bit register or memorylocation by 1.DEC reg1648 +rwDecrement the contents of a 16-bit register by 1.(See “REX Prefixes” on page 11.)DEC reg3248 +rdDecrement the contents of a 32-bit register by 1.(See “REX Prefixes” on page 11.)Related InstructionsINC, SUBInstruction ReferenceDEC107AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFMMMM7642CF0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded the data segment limit or wasnon-canonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.108DECInstruction Reference24594—Rev.
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