Volume 3 General-Purpose and System Instructions (794097), страница 20
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3.13—July 2007IF (OPCODE = callf [mem])//CALLF Indirect{temp_offset = READ_MEM.z [mem]temp_sel= READ_MEM.w [mem+Z]}ELSE // (OPCODE = callf direct){IF (64BIT_MODE)EXCEPTION [#UD]// ’CALLF direct’ is illegal in 64-bit mode.temp_offset = z-sized offset specified in the instructionzero-extended to 64 bitstemp_sel= selector specified in the instruction}temp_desc = READ_DESCRIPTOR (temp_sel, cs_chk)IF (temp_desc.attr.type = ’available_tss’)TASK_SWITCH// Using temp_sel as the target TSS selector.ELSIF (temp_desc.attr.type = ’taskgate’)TASK_SWITCH// Using the TSS selector in the task gate// as the target TSS.ELSIF (temp_desc.attr.type = ’code’)// If the selector refers to a code descriptor, then// the offset we read is the target RIP.{temp_RIP = temp_offsetCS = temp_descPUSH.v old_CSPUSH.v next_RIPIF ((!64BIT_MODE) && (temp_RIP > CS.limit))// temp_RIP can’t be non-canonical becauseEXCEPTION [#GP(0)]// it’s a 16- or 32-bit offset, zero-extended// to 64 bits.RIP = temp_RIPEXIT}ELSE// (temp_desc.attr.type = ’callgate’)// If the selector refers to a call gate, then// the target CS and RIP both come from the call gate.{IF (LONG_MODE)// The size of the gate controls the size of the stack pushes.V=8-byte// Long mode only uses 64-bit call gates, force 8-byte opsize.ELSIF (temp_desc.attr.type = ’callgate32’)V=4-byte// Legacy mode, using a 32-bit call-gate, force 4-byte opsize.ELSE// (temp_desc.attr.type = ’callgate16’)V=2-byte// Legacy mode, using a 16-bit call-gate, force 2-byte opsize.80CALL (Far)Instruction Reference24594—Rev.
3.13—July 2007AMD64 Technologytemp_RIP = temp_desc.offsetIF (LONG_MODE)// In long mode, we need to read the 2nd half of a// 16-byte call-gate from the GDT/LDT, to get the upper// 32 bits of the target RIP.{temp_upper = READ_MEM.q [temp_sel+8]IF (temp_upper’s extended attribute bits != 0)EXCEPTION [#GP(temp_sel)]temp_RIP = tempRIP + (temp_upper SHL 32)// Concatenate both halves of RIP}CS = READ_DESCRIPTOR (temp_desc.segment, clg_chk)IF (CS.attr.conforming=1)temp_CPL = CPLELSEtemp_CPL = CS.attr.dplIF (CPL=temp_CPL){PUSH.v old_CSPUSH.v next_RIPIF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit)){EXCEPTION[#GP(0)]}RIP = temp_RIPEXIT}ELSE // (CPL != temp_CPL), Changing privilege level.{CPL = temp_CPLtemp_ist = 0// Call-far doesn’t use ist pointers.temp_SS_desc:temp_RSP = READ_INNER_LEVEL_STACK_POINTER (CPL, temp_ist)RSP.q = temp_RSPSS = temp_SS_descPUSH.v old_SS// #SS on this and following pushes use// SS.sel as error code.PUSH.v old_RSPIF (LEGACY_MODE)// Legacy-mode call gates have{// a param_count field.temp_PARAM_COUNT = temp_desc.attr.param_countFOR (I=temp_PARAM_COUNT; I>0; I--)Instruction ReferenceCALL (Far)81AMD64 Technology24594—Rev.
3.13—July 2007{temp_DATA = READ_MEM.v [old_SS:(old_RSP+I*V)]PUSH.v temp_DATA}}PUSH.v old_CSPUSH.v next_RIPIF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit)){EXCEPTION [#GP(0)]}RIP = temp_RIPEXIT}}Related InstructionsCALL (Near), RET (Near), RET (Far)rFLAGS AffectedNone, unless a task switch occurs, in which case all flags are modified.ExceptionsExceptionInvalid opcode, #UDInvalid TSS, #TS(selector)Segment notpresent, #NP(selector)82VirtualReal 8086 ProtectedXXCause of ExceptionXThe far CALL indirect opcode (FF /3) had a register operand.XThe far CALL direct opcode (9A) was executed in 64-bit mode.XAs part of a stack switch, the target stack segment selector orrSP in the TSS was beyond the TSS limit.XAs part of a stack switch, the target stack segment selector inthe TSS was a null selector.XAs part of a stack switch, the target stack selector’s TI bit wasset, but LDT selector was a null selector.XAs part of a stack switch, the target stack segment selector inthe TSS was beyond the limit of the GDT or LDT descriptortable.XAs part of a stack switch, the target stack segment selector inthe TSS contained a RPL that was not equal to its DPL.XAs part of a stack switch, the target stack segment selector inthe TSS contained a DPL that was not equal to the CPL of thecode segment selector.XAs part of a stack switch, the target stack segment selector inthe TSS was not a writable segment.XThe accessed code segment, call gate, task gate, or TSS wasnot present.CALL (Far)Instruction Reference24594—Rev.
3.13—July 2007ExceptionStack, #SSVirtualReal 8086 ProtectedXXStack, #SS(selector)General protection,#GPAMD64 TechnologyCause of ExceptionXA memory address exceeded the stack segment limit or wasnon-canonical, and no stack switch occurred.XAfter a stack switch, a memory access exceeded the stacksegment limit or was non-canonical.XAs part of a stack switch, the SS register was loaded with anon-null segment selector and the segment was marked notpresent.XXXA memory address exceeded a data segment limit or was noncanonical.XXXThe target offset exceeded the code segment limit or was noncanonical.XA null data segment was used to reference memory.XThe target code segment selector was a null selector.XA code, call gate, task gate, or TSS descriptor exceeded thedescriptor table limit.XA segment selector’s TI bit was set but the LDT selector was anull selector.XThe segment descriptor specified by the instruction was not acode segment, task gate, call gate or available TSS in legacymode, or not a 64-bit code segment or a 64-bit call gate in longmode.XThe RPL of the non-conforming code segment selectorspecified by the instruction was greater than the CPL, or itsDPL was not equal to the CPL.XThe DPL of the conforming code segment descriptor specifiedby the instruction was greater than the CPL.XThe DPL of the callgate, taskgate, or TSS descriptor specifiedby the instruction was less than the CPL, or less than its ownRPL.XThe segment selector specified by the call gate or task gatewas a null selector.XThe segment descriptor specified by the call gate was not acode segment in legacy mode, or not a 64-bit code segment inlong mode.XThe DPL of the segment descriptor specified by the call gatewas greater than the CPL.XThe 64-bit call gate’s extended attribute bits were not zero.XThe TSS descriptor was found in the LDT.General protection,#GP(selector)Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceCALL (Far)83AMD64 Technology24594—Rev.
3.13—July 2007CBWCWDECDQEConvert to Sign-ExtendedCopies the sign bit in the AL or eAX register to the upper bits of the rAX register. The effect of thisinstruction is to convert a signed byte, word, or doubleword in the AL or eAX register into a signedword, doubleword, or double quadword in the rAX register.
This action helps avoid overflow problemsin signed number arithmetic.The CDQE mnemonic is meaningful only in 64-bit mode.MnemonicOpcodeDescriptionCBW98Sign-extend AL into AX.CWDE98Sign-extend AX into EAX.CDQE98Sign-extend EAX into RAX.Related InstructionsCWD, CDQ, CQOrFLAGS AffectedNoneExceptionsNone84CBW, CWDE, CDQEInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyCWDCDQCQOConvert to Sign-ExtendedCopies the sign bit in the rAX register to all bits of the rDX register. The effect of this instruction is toconvert a signed word, doubleword, or quadword in the rAX register into a signed doubleword,quadword, or double-quadword in the rDX:rAX registers. This action helps avoid overflow problemsin signed number arithmetic.The CQO mnemonic is meaningful only in 64-bit mode.MnemonicOpcodeDescriptionCWD99Sign-extend AX into DX:AX.CDQ99Sign-extend EAX into EDX:EAX.CQO99Sign-extend RAX into RDX:RAX.Related InstructionsCBW, CWDE, CDQErFLAGS AffectedNoneExceptionsNoneInstruction ReferenceCWD, CDQ, CQO85AMD64 Technology24594—Rev.
3.13—July 2007CLCClear Carry FlagClears the carry flag (CF) in the rFLAGS register to zero.MnemonicOpcodeCLCDescriptionF8Clear the carry flag (CF) to zero.Related InstructionsSTC, CMCrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF02120191817161413–1211109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsNone86CLCInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyCLDClear Direction FlagClears the direction flag (DF) in the rFLAGS register to zero.
If the DF flag is 0, each iteration of astring instruction increments the data pointer (index registers rSI or rDI). If the DF flag is 1, the stringinstruction decrements the pointer. Use the CLD instruction before a string instruction to make the datapointer increment.MnemonicOpcodeCLDDescriptionFCClear the direction flag (DF) to zero.Related InstructionsCMPSx, INSx, LODSx, MOVSx, OUTSx, SCASx, STD, STOSxrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF987642002120191817161413–121110Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank.
Undefined flags are U.ExceptionsNoneInstruction ReferenceCLD87AMD64 Technology24594—Rev. 3.13—July 2007CLFLUSHCache Line FlushFlushes the cache line specified by the mem8 linear-address. The instruction checks all levels of thecache hierarchy—internal caches and external caches—and invalidates the cache line in every cache inwhich it is found. If a cache contains a dirty copy of the cache line (that is, the cache line is in themodified or owned MOESI state), the line is written back to memory before it is invalidated. Theinstruction sets the cache-line MOESI state to invalid.The instruction also checks the physical address corresponding to the linear-address operand againstthe processor’s write-combining buffers. If the write-combining buffer holds data intended for thatphysical address, the instruction writes the entire contents of the buffer to memory.
This occurs eventhough the data is not cached in the cache hierarchy. In a multiprocessor system, the instruction checksthe write-combining buffers only on the processor that executed the CLFLUSH instruction.The CLFLUSH instruction is weakly-ordered with respect to other instructions that operate onmemory. Speculative loads initiated by the processor, or specified explicitly using cache-prefetchinstructions, can be reordered around a CLFLUSH instruction.
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