Volume 3 General-Purpose and System Instructions (794097), страница 17
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3.13—July 2007MnemonicOpcodeDescriptionAND reg/mem16, reg1621 /rAND the contents of a 16-bit register or memorylocation with the contents of a 16-bit register.AND reg/mem32, reg3221 /rAND the contents of a 32-bit register or memorylocation with the contents of a 32-bit register.AND reg/mem64, reg6421 /rAND the contents of a 64-bit register or memorylocation with the contents of a 64-bit register.AND reg8, reg/mem822 /rAND the contents of an 8-bit register with the contentsof an 8-bit memory location or register.AND reg16, reg/mem1623 /rAND the contents of a 16-bit register with the contentsof a 16-bit memory location or register.AND reg32, reg/mem3223 /rAND the contents of a 32-bit register with the contentsof a 32-bit memory location or register.AND reg64, reg/mem6423 /rAND the contents of a 64-bit register with the contentsof a 64-bit memory location or register.Related InstructionsTEST, OR, NOT, NEG, XORrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTF02120191817161413–12111098SFZFAFPFCFMMUM076420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.62ANDInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyBOUNDCheck Array BoundChecks whether an array index (first operand) is within the bounds of an array (second operand). Thearray index is a signed integer in the specified register.
If the operand-size attribute is 16, the arrayoperand is a memory location containing a pair of signed word-integers; if the operand-size attribute is32, the array operand is a pair of signed doubleword-integers. The first word or doubleword specifiesthe lower bound of the array and the second word or doubleword specifies the upper bound.The array index must be greater than or equal to the lower bound and less than or equal to the upperbound.
If the index is not within the specified bounds, the processor generates a BOUND rangeexceeded exception (#BR).The bounds of an array, consisting of two words or doublewords containing the lower and upper limitsof the array, usually reside in a data structure just before the array itself, making the limits addressablethrough a constant offset from the beginning of the array.
With the address of the array in a register,this practice reduces the number of bus cycles required to determine the effective address of the arraybounds.Using this instruction in 64-bit mode generates an invalid-opcode exception.MnemonicOpcodeDescriptionBOUND reg16, mem16&mem1662 /rTest whether a 16-bit array index is within the boundsspecified by the two 16-bit values in mem16&mem16.(Invalid in 64-bit mode.)BOUND reg32, mem32&mem3262 /rTest whether a 32-bit array index is within the boundsspecified by the two 32-bit values in mem32&mem32.(Invalid in 64-bit mode.)Related InstructionsINT, INT3, INTOrFLAGS AffectedNoneExceptionsExceptionBound range, #BRInvalid opcode, #UDVirtualReal 8086 ProtectedCause of ExceptionXXXThe bound range was exceeded.XXXThe source operand was a register.XInstruction was executed in 64-bit mode.Stack, #SSXXXA memory address exceeded the stack segment limitGeneral protection,#GPXXXA memory address exceeded a data segment limit.XA null data segment was used to reference memory.Instruction ReferenceBOUND63AMD64 TechnologyException24594—Rev.
3.13—July 2007VirtualReal 8086 ProtectedCause of ExceptionPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.64BOUNDInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyBSFBit Scan ForwardSearches the value in a register or a memory location (second operand) for the least-significant set bit.If a set bit is found, the instruction clears the zero flag (ZF) and stores the index of the least-significantset bit in a destination register (first operand). If the second operand contains 0, the instruction sets ZFto 1 and does not change the contents of the destination register.
The bit index is an unsigned offsetfrom bit 0 of the searched value.MnemonicOpcodeDescriptionBSF reg16, reg/mem160F BC /rBit scan forward on the contents of reg/mem16.BSF reg32, reg/mem320F BC /rBit scan forward on the contents of reg/mem32.BSF reg64, reg/mem640F BC /rBit scan forward on the contents of reg/mem64Related InstructionsBSRrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFUMUUU76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceBSF65AMD64 Technology24594—Rev.
3.13—July 2007BSRBit Scan ReverseSearches the value in a register or a memory location (second operand) for the most-significant set bit.If a set bit is found, the instruction clears the zero flag (ZF) and stores the index of the most-significantset bit in a destination register (first operand). If the second operand contains 0, the instruction sets ZFto 1 and does not change the contents of the destination register. The bit index is an unsigned offsetfrom bit 0 of the searched value.MnemonicOpcodeDescriptionBSR reg16, reg/mem160F BD /rBit scan reverse on the contents of reg/mem16.BSR reg32, reg/mem320F BD /rBit scan reverse on the contents of reg/mem32.BSR reg64, reg/mem640F BD /rBit scan reverse on the contents of reg/mem64.Related InstructionsBSFrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFUMUUU76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded the data segment limit or wasnon-canonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.66BSRInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyBSWAPByte SwapReverses the byte order of the specified register.
This action converts the contents of the register fromlittle endian to big endian or vice versa. In a doubleword, bits 7–0 are exchanged with bits 31–24, andbits 15–8 are exchanged with bits 23–16. In a quadword, bits 7–0 are exchanged with bits 63–56, bits15–8 with bits 55–48, bits 23–16 with bits 47–40, and bits 31–24 with bits 39–32. A subsequent use ofthe BSWAP instruction with the same operand restores the original value of the operand.The result of applying the BSWAP instruction to a 16-bit register is undefined. To swap the bytes of a16-bit register, use the XCHG instruction and specify the respective byte halves of the 16-bit registeras the two operands. For example, to swap the bytes of AX, use XCHG AL, AH.MnemonicOpcodeDescriptionBSWAP reg320F C8 +rdReverse the byte order of reg32.BSWAP reg640F C8 +rqReverse the byte order of reg64.Related InstructionsXCHGrFLAGS AffectedNoneExceptionsNoneInstruction ReferenceBSWAP67AMD64 Technology24594—Rev.
3.13—July 2007BTBit TestCopies a bit, specified by a bit index in a register or 8-bit immediate value (second operand), from a bitstring (first operand), also called the bit base, to the carry flag (CF) of the rFLAGS register.If the bit base operand is a register, the instruction uses the modulo 16, 32, or 64 (depending on theoperand size) of the bit index to select a bit in the register.If the bit base operand is a memory location, bit 0 of the byte at the specified address is the bit base ofthe bit string.
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