Volume 3 General-Purpose and System Instructions (794097), страница 14
Текст из файла (страница 14)
Thedigit is specified by the ModRM reg field and is used as an instruction-opcode extension. Validdigit values range from 0 to 7./r—Indicates that the ModRM byte specifies both a register operand and a reg/mem (register ormemory) operand.cb, cw, cd, cp—Specifies a code-offset value and possibly a new code-segment register value. Thevalue following the opcode is either one byte (cb), two bytes (cw), four bytes (cd), or six bytes (cp).Instruction Overview39AMD64 Technology••••24594—Rev. 3.13—July 2007ib, iw, id—Specifies an immediate-operand value.
The opcode determines whether the value issigned or unsigned. The value following the opcode, ModRM, or SIB byte is either one byte (ib),two bytes (iw), or four bytes (id). Word and doubleword values start with the low-order byte.+rb, +rw, +rd, +rq—Specifies a register value that is added to the hexadecimal byte on the left,forming a one-byte opcode.
The result is an instruction that operates on the register specified by theregister code. Valid register-code values are shown in Table 2-2.m64—Specifies a quadword (64-bit) operand in memory.+i—Specifies an x87 floating-point stack operand, ST(i). The value is used only with x87 floatingpoint instructions. It is added to the hexadecimal byte on the left, forming a one-byte opcode.
Validvalues range from 0 to 7.Table 2-2.REX.BBit10or no REXPrefix+rb, +rw, +rd, and +rq Register ValueValue+rb+rw+rd+rq0ALAXEAXRAX1CLCXECXRCX2DLDXEDXRDX3BL45671Specified RegisterAH,BXEBXRBXSPL1SPESPRSP1BPEBPRBP1SIESIRSIDIL1DIEDIRDICH, BPLDH, SILBH,0R8BR8WR8DR81R9BR9WR9DR92R10BR10WR10DR103R11BR11WR11DR114R12BR12WR12DR125R13BR13WR13DR136R14BR14WR14DR147R15BR15WR15DR151. See “REX Prefixes” on page 11.40Instruction Overview24594—Rev.
3.13—July 2007AMD64 Technology2.5.3 Pseudocode DefinitionsPseudocode examples are given for the actions of several complex instructions (for example, see“CALL (Near)” on page 76). The following definitions apply to all such pseudocode examples://///////////////////////////////////////////////////////////////////////////////// Basic Definitions/////////////////////////////////////////////////////////////////////////////////// All comments start with these double slashes.REAL_MODE= (cr0.pe=0)PROTECTED_MODE = ((cr0.pe=1) && (rflags.vm=0))VIRTUAL_MODE= ((cr0.pe=1) && (rflags.vm=1))LEGACY_MODE= (efer.lma=0)LONG_MODE= (efer.lma=1)64BIT_MODE= ((efer.lma=1) && (cs.L=1) && (cs.d=0))COMPATIBILITY_MODE = (efer.lma=1) && (cs.L=0)PAGING_ENABLED = (cr0.pg=1)ALIGNMENT_CHECK_ENABLED = ((cr0.am=1) && (eflags.ac=1) &&CPL= the current privilege level (0-3)OPERAND_SIZE= 16, 32, or 64 (depending on current codeADDRESS_SIZE= 16, 32, or 64 (depending on current codeSTACK_SIZE= 16, 32, or 64 (depending on current code(cpl=3))and 66h/rex prefixes)and 67h prefixes)and SS.attr.B)old_RIPold_RSPold_RFLAGSold_CSold_DSold_ESold_FSold_GSold_SS=========RIP at the start of current instructionRSP at the start of current instructionRFLAGS at the start of the instructionCS selector at the start of current instructionDS selector at the start of current instructionES selector at the start of current instructionFS selector at the start of current instructionGS selector at the start of current instructionSS selector at the start of current instructionRIPRSPRBPRFLAGSnext_RIP=====thethethetheRIPCS= thesel= theselSSSRCDESTtemp_*current RIP registercurrent RSP registercurrent RBP registercurrent RFLAGS registerat start of next instructioncurrent CSbase limitcurrent SSbase limitdescriptor, including the subfields:attrdescriptor, including the subfields:attr= the instruction’s Source operand= the instruction’s Destination operand// 64-bit temporary registerInstruction Overview41AMD64 Technology24594—Rev.
3.13—July 2007temp_*_desc// temporary descriptor, with subfields://if it points to a block of memory: sel base limit attr//if it’s a gate descriptor: sel offset segment attrNULL = 0x0000// null selector is all zeros// V,Z,A,S are integer variables, assigned a value when an instruction begins// executing (they can be assigned a different value in the middle of an// instruction, if needed)V = 2 if OPERAND_SIZE=164 if OPERAND_SIZE=328 if OPERAND_SIZE=64Z = 2 if OPERAND_SIZE=164 if OPERAND_SIZE=324 if OPERAND_SIZE=64A = 2 if ADDRESS_SIZE=164 if ADDRESS_SIZE=328 if ADDRESS_SIZE=64S = 2 if STACK_SIZE=164 if STACK_SIZE=328 if STACK_SIZE=64/////////////////////////////////////////////////////////////////////////////////// Bit Range Inside a Register/////////////////////////////////////////////////////////////////////////////////temp_data.[X:Y]// Bit X through Y in temp_data, with the other bits// in the register masked off./////////////////////////////////////////////////////////////////////////////////// Moving Data From One Register To Another/////////////////////////////////////////////////////////////////////////////////temp_dest.b = temp_src// 1-byte move (copies lower 8 bits of temp_src to// temp_dest, preserving the upper 56 bits of temp_dest)temp_dest.w = temp_src// 2-byte move (copies lower 16 bits of temp_src to// temp_dest, preserving the upper 48 bits of temp_dest)temp_dest.d = temp_src// 4-byte move (copies lower 32 bits of temp_src to// temp_dest, and zeros out the upper 32 bits of temp_dest)temp_dest.q = temp_src// 8-byte move (copies all 64 bits of temp_src to// temp_dest)temp_dest.v = temp_src42// 2-byte move if V=2,// 4-byte move if V=4,// 8-byte move if V=8Instruction Overview24594—Rev.
3.13—July 2007AMD64 Technologytemp_dest.z = temp_src// 2-byte move if Z=2,// 4-byte move if Z=4temp_dest.a = temp_src// 2-byte move if A=2,// 4-byte move if A=4,// 8-byte move if A=8temp_dest.s = temp_src// 2-byte move if S=2,// 4-byte move if S=4,// 8-byte move if S=8/////////////////////////////////////////////////////////////////////////////////// Bitwise Operations/////////////////////////////////////////////////////////////////////////////////temptemptemptemptemptemp======a AND ba OR ba XOR bNOT aa SHL ba SHR b/////////////////////////////////////////////////////////////////////////////////// Logical Operations/////////////////////////////////////////////////////////////////////////////////IFIFIFIFIFIFIFIF(FOO(FOO(FOO(FOO(FOO(FOO(FOO(FOO&& BAR)|| BAR)= BAR)!= BAR)> BAR)< BAR)>= BAR)<= BAR)/////////////////////////////////////////////////////////////////////////////////// IF-THEN-ELSE/////////////////////////////////////////////////////////////////////////////////IF (FOO)...IF (FOO)...ELSIF (BAR)...ELSEInstruction Overview43AMD64 Technology24594—Rev.
3.13—July 2007...IF ((FOO && BAR) || (CONE && HEAD)).../////////////////////////////////////////////////////////////////////////////////// Exceptions/////////////////////////////////////////////////////////////////////////////////EXCEPTION [#GP(0)]EXCEPTION [#UD]// error code in parenthesis// if no error codepossible exception types:#DE#DB#BP#OF#BR#UD#NM#DF#TS#NP#SS#GP#PF#MF#AC#MC#XF//////////////////////////////////Divide-By-Zero-Error Exception (Vector 0)Debug Exception (Vector 1)INT3 Breakpoint Exception (Vector 3)INTO Overflow Exception (Vector 4)Bound-Range Exception (Vector 5)Invalid-Opcode Exception (Vector 6)Device-Not-Available Exception (Vector 7)Double-Fault Exception (Vector 8)Invalid-TSS Exception (Vector 10)Segment-Not-Present Exception (Vector 11)Stack Exception (Vector 12)General-Protection Exception (Vector 13)Page-Fault Exception (Vector 14)x87 Floating-Point Exception-Pending (Vector 16)Alignment-Check Exception (Vector 17)Machine-Check Exception (Vector 18)SIMD Floating-Point Exception (Vector 19)/////////////////////////////////////////////////////////////////////////////////// READ_MEM// General memory read.
This zero-extends the data to 64 bits and returns it./////////////////////////////////////////////////////////////////////////////////usage:temp = READ_MEM.x [seg:offset]// where x is one of {v, z, b, w, d, q}// and denotes the size of the memory readdefinition:IF ((seg AND 0xFFFC) = NULL)// GP fault for using a null segment to// reference memoryEXCEPTION [#GP(0)]IF ((seg=CS) || (seg=DS) || (seg=ES) || (seg=FS) || (seg=GS))// CS,DS,ES,FS,GS check for segment limit or canonical44Instruction Overview24594—Rev.
3.13—July 2007AMD64 TechnologyIF ((!64BIT_MODE) && (offset is outside seg’s limit))EXCEPTION [#GP(0)]// #GP fault for segment limit violation in non-64-bit modeIF ((64BIT_MODE) && (offset is non-canonical))EXCEPTION [#GP(0)]// #GP fault for non-canonical address in 64-bit modeELSIF (seg=SS)// SS checks for segment limit or canonicalIF ((!64BIT_MODE) && (offset is outside seg’s limit))EXCEPTION [#SS(0)]// stack fault for segment limit violation in non-64-bit modeIF ((64BIT_MODE) && (offset is non-canonical))EXCEPTION [#SS(0)]// stack fault for non-canonical address in 64-bit modeELSE // ((seg=GDT) || (seg=LDT) || (seg=IDT) || (seg=TSS))// GDT,LDT,IDT,TSS check for segment limit and canonicalIF (offset > seg.limit)EXCEPTION [#GP(0)] // #GP fault for segment limit violation// in all modesIF ((LONG_MODE) && (offset is non-canonical))EXCEPTION [#GP(0)] // #GP fault for non-canonical address in long modeIF ((ALIGNMENT_CHECK_ENABLED) && (offset misaligned, considering itssize and alignment))EXCEPTION [#AC(0)]IF ((64_bit_mode) && ((seg=CS) || (seg=DS) || (seg=ES) || (seg=SS))temp_linear = offsetELSEtemp_linear = seg.base + offsetIF ((PAGING_ENABLED) && (virtual-to-physical translation for temp_linearresults in a page-protection violation))EXCEPTION [#PF(error_code)] // page fault for page-protection violation// (U/S violation, Reserved bit violation)IF ((PAGING_ENABLED) && (temp_linear is on a not-present page))EXCEPTION [#PF(error_code)] // page fault for not-present pagetemp_data = memory [temp_linear].x// zero-extends the data to 64// bits, and saves it in temp_dataRETURN (temp_data)// return the zero-extended data/////////////////////////////////////////////////////////////////////////////////// WRITE_MEM // General memory write/////////////////////////////////////////////////////////////////////////////////usage:WRITE_MEM.x [seg:offset] = temp.xInstruction Overview// where <X> is one of these:// {V, Z, B, W, D, Q} and denotes the45AMD64 Technology24594—Rev.
3.13—July 2007// size of the memory writedefinition:IF ((seg & 0xFFFC)= NULL)// GP fault for using a null segment// to reference memoryEXCEPTION [#GP(0)]IF (seg isn’t writable)EXCEPTION [#GP(0)]// GP fault for writing to a read-only segmentIF ((seg=CS) || (seg=DS) || (seg=ES) || (seg=FS) || (seg=GS))// CS,DS,ES,FS,GS check for segment limit or canonicalIF ((!64BIT_MODE) && (offset is outside seg’s limit))EXCEPTION [#GP(0)]// #GP fault for segment limit violation in non-64-bit modeIF ((64BIT_MODE) && (offset is non-canonical))EXCEPTION [#GP(0)]// #GP fault for non-canonical address in 64-bit modeELSIF (seg=SS)// SS checks for segment limit or canonicalIF ((!64BIT_MODE) && (offset is outside seg’s limit))EXCEPTION [#SS(0)]// stack fault for segment limit violation in non-64-bit modeIF ((64BIT_MODE) && (offset is non-canonical))EXCEPTION [#SS(0)]// stack fault for non-canonical address in 64-bit modeELSE // ((seg=GDT) || (seg=LDT) || (seg=IDT) || (seg=TSS))// GDT,LDT,IDT,TSS check for segment limit and canonicalIF (offset > seg.limit)EXCEPTION [#GP(0)]// #GP fault for segment limit violation in all modesIF ((LONG_MODE) && (offset is non-canonical))EXCEPTION [#GP(0)]// #GP fault for non-canonical address in long modeIF ((ALIGNMENT_CHECK_ENABLED) && (offset is misaligned, consideringits size and alignment))EXCEPTION [#AC(0)]IF ((64_bit_mode) && ((seg=CS) || (seg=DS) || (seg=ES) || (seg=SS))temp_linear = offsetELSEtemp_linear = seg.base + offsetIF ((PAGING_ENABLED) && (the virtual-to-physical translation fortemp_linear results in a page-protection violation)){EXCEPTION [#PF(error_code)]// page fault for page-protection violation// (U/S violation, Reserved bit violation)}46Instruction Overview24594—Rev.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
