Volume 3 General-Purpose and System Instructions (794097), страница 11
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3.13—July 2007Bits:765mod432reg10ModRMr/mREX.R bit of REX prefix canextend this field to 4 bitsREX.B bit of REX prefix canextend this field to 4 bits513-305.epsFigure 1-4. ModRM-Byte FormatIn some instructions, the ModRM byte is followed by an SIB byte, which defines memory addressingfor the complex-addressing modes described in “Effective Addresses” in Volume 1. The SIB byte hasthree fields—scale, index, and base—that define the scale factor, index-register number, and baseregister number for 32-bit and 64-bit complex addressing modes. In 64-bit mode, the REX.B andREX.X bits extend the encoding of the SIB byte’s base and index fields.Figure 1-5 shows the format of an SIB byte.Bits:7scale654index321base0SIBREX.X bit of REX prefix canextend this field to 4 bits513-306.epsREX.B bit of REX prefix canextend this field to 4 bitsFigure 1-5.
SIB-Byte FormatThe encodings of ModRM and SIB bytes not only define memory-addressing modes, but they alsospecify operand registers. The encodings do this by using 3-bit fields in the ModRM and SIB bytes,depending on the format:••18ModRM: the reg and r/m fields of the ModRM byte. (Case 1 in Figure 1-3 on page 15 shows anexample of this).ModRM with SIB: the reg field of the ModRM byte and the base and index fields of the SIB byte.(Case 3 in Figure 1-3 on page 15 shows an example of this).Instruction Formats24594—Rev. 3.13—July 2007•AMD64 TechnologyInstructions without ModRM: the reg field of the opcode. (Case 4 in Figure 1-3 on page 15 showsan example of this).In 64-bit mode, the bits needed to extend each field for accessing the additional registers are providedby the REX prefixes, as shown in Figure 1-4 and Figure 1-5.For details on opcode encoding, see Appendix A, “Opcode and Operand Encodings.”1.5Displacement BytesA displacement (also called an offset) is a signed value that is added to the base of a code segment(absolute addressing) or to an instruction pointer (relative addressing), depending on the addressingmode.
The size of a displacement is 1, 2, or 4 bytes. If an addressing mode requires a displacement, thebytes (1, 2, or 4) for the displacement follow the opcode, ModRM, or SIB byte (whichever comes last)in the instruction encoding.In 64-bit mode, the same ModRM and SIB encodings are used to specify displacement sizes as thoseused in legacy and compatibility modes. However, the displacement is sign-extended to 64 bits duringeffective-address calculations. Also, in 64-bit mode, support is provided for some 64-bit displacementand immediate forms of the MOV instruction. See “Immediate Operand Size” in Volume 1 for moreinformation on this.1.6Immediate BytesAn immediate is a value—typically an operand value—encoded directly into the instruction.Depending on the opcode and the operating mode, the size of an immediate operand can be 1, 2, 4, or 8bytes.
64-bit immediates are allowed in 64-bit mode on MOV instructions that load GPRs, otherwisethey are limited to 4 bytes. See “Immediate Operand Size” in Volume 1 for more information.If an instruction takes an immediate operand, the bytes (1, 2, 4, or 8) for the immediate follow theopcode, ModRM, SIB, or displacement bytes (whichever come last) in the instruction encoding. Some128-bit media instructions use the immediate byte as a condition code.1.7RIP-Relative AddressingIn 64-bit mode, addressing relative to the contents of the 64-bit instruction pointer (programcounter)—called RIP-relative addressing or PC-relative addressing—is implemented for certaininstructions.
In such cases, the effective address is formed by adding the displacement to the 64-bit RIPof the next instruction.In the legacy x86 architecture, addressing relative to the instruction pointer is available only in controltransfer instructions. In the 64-bit mode, any instruction that uses ModRM addressing can use RIPrelative addressing. This feature is particularly useful for addressing data in position-independent codeand for code that addresses global data.Instruction Formats19AMD64 Technology24594—Rev.
3.13—July 2007Without RIP-relative addressing, ModRM instructions address memory relative to zero. With RIPrelative addressing, ModRM instructions can address memory relative to the 64-bit RIP using a signed32-bit displacement. This provides an offset range of ±2 Gbytes from the RIP.Programs usually have many references to data, especially global data, that are not register-based.
Toload such a program, the loader typically selects a location for the program in memory and then adjustsprogram references to global data based on the load location. RIP-relative addressing of data makesthis adjustment unnecessary.1.7.1 EncodingTable 1-13 shows the ModRM and SIB encodings for RIP-relative addressing. Redundant forms of 32bit displacement-only addressing exist in the current ModRM and SIB encodings. There is oneModRM encoding with several SIB encodings.
RIP-relative addressing is encoded using one of theredundant forms. In 64-bit mode, the ModRM Disp32 (32-bit displacement) encoding is redefined tobe RIP + Disp32 rather than displacement-only.Table 1-13. Encoding for RIP-Relative AddressingModRM and SIBEncodingsMeaning in Legacy andCompatibility ModesMeaning in 64-bit ModeDisp32RIP + Disp32Zero-based (normal)displacement addressingmust use SIB form (seenext row).If mod = 00, Disp32Same as LegacyNoneModRM Byte:• mod = 00• r/m = 101 (none)Additional 64-bitImplicationsSIB Byte:• base = 101 (none)• index = 100 (none)• scale = 1, 2, 4,81.7.2 REX Prefix and RIP-Relative AddressingModRM encoding for RIP-relative addressing does not depend on a REX prefix.
In particular, the r/mencoding of 101, used to select RIP-relative addressing, is not affected by the REX prefix. Forexample, selecting R13 (REX.B = 1, r/m = 101) with mod = 00 still results in RIP-relative addressing.The four-bit r/m field of ModRM is not fully decoded. Therefore, in order to address R13 with nodisplacement, software must encode it as R13 + 0 using a one-byte displacement of zero.1.7.3 Address-Size Prefix and RIP-Relative AddressingRIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. Conversely, use of theaddress-size prefix (“Address-Size Override Prefix” on page 6) does not disable RIP-relativeaddressing.
The effect of the address-size prefix is to truncate and zero-extend the computed effectiveaddress to 32 bits, like any other addressing mode.20Instruction Formats24594—Rev. 3.13—July 20072Instruction Overview2.1Instruction SubsetsAMD64 TechnologyFor easier reference, the instruction descriptions are divided into five instruction subsets. Thefollowing sections describe the function, mnemonic syntax, opcodes, affected flags, and possibleexceptions generated by all instructions in the AMD64 architecture:•••••Chapter 3, “General-Purpose Instruction Reference”—The general-purpose instructions are usedin basic software execution. Most of these load, store, or operate on data in the general-purposeregisters (GPRs), in memory, or in both. Other instructions are used to alter sequential programflow by branching to other locations within the program or to entirely different programs.Chapter 4, “System Instruction Reference”—The system instructions establish the processoroperating mode, access processor resources, handle program and system errors, and managememory.“128-Bit Media Instruction Reference” in Volume 4—The 128-bit media instructions load, store,or operate on data located in the 128-bit XMM registers.
These instructions define both vector andscalar operations on floating-point and integer data types. They include the SSE and SSE2instructions that operate on the XMM registers. Some of these instructions convert sourceoperands in XMM registers to destination operands in GPR, MMX, or x87 registers or otherwiseaffect XMM state.“64-Bit Media Instruction Reference” in Volume 5—The 64-bit media instructions load, store, oroperate on data located in the 64-bit MMX registers. These instructions define both vector andscalar operations on integer and floating-point data types.
They include the legacy MMX™instructions, the 3DNow!™ instructions, and the AMD extensions to the MMX and 3DNow!instruction sets. Some of these instructions convert source operands in MMX registers todestination operands in GPR, XMM, or x87 registers or otherwise affect MMX state.“x87 Floating-Point Instruction Reference” in Volume 5—The x87 instructions are used in legacyfloating-point applications. Most of these instructions load, store, or operate on data located in thex87 ST(0)–ST(7) stack registers (the FPR0–FPR7 physical registers). The remaining instructionswithin this category are used to manage the x87 floating-point environment.The description of each instruction covers its behavior in all operating modes, including legacy mode(real, virtual-8086, and protected modes) and long mode (compatibility and 64-bit modes). Details ofcertain kinds of complex behavior—such as control-flow changes in CALL, INT, or FXSAVEinstructions—have cross-references in the instruction-detail pages to detailed descriptions in volumes1 and 2.Two instructions—CMPSD and MOVSD—use the same mnemonic for different instructions.Assemblers can distinguish them on the basis of the number and type of operands with which they areused.Instruction Overview21AMD64 Technology2.224594—Rev.
3.13—July 2007Reference-Page FormatFigure 2-1 on page 23 shows the format of an instruction-detail page. The instruction mnemonic isshown in bold at the top-left, along with its name. In this example, POPFD is the mnemonic and POPto EFLAGS Doubleword is the name. Next, there is a general description of the instruction’s operation.Many descriptions have cross-references to more detail in other parts of the manual.Beneath the general description, the mnemonic is shown again, together with the related opcode(s) anda description summary.
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