Volume 3 General-Purpose and System Instructions (794097), страница 6
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The high-order bit is shown first.128-bit media instructionsInstructions that use the 128-bit XMM registers. These are a combination of the SSE and SSE2instruction sets.64-bit media instructionsInstructions that use the 64-bit MMX registers. These are primarily a combination of MMX™ and3DNow!™ instruction sets, with some additional instructions from the SSE and SSE2 instructionsets.16-bit modeLegacy mode or compatibility mode in which a 16-bit address size is active. See legacy mode andcompatibility mode.xviPreface24594—Rev.
3.13—July 2007AMD64 Technology32-bit modeLegacy mode or compatibility mode in which a 32-bit address size is active. See legacy mode andcompatibility mode.64-bit modeA submode of long mode. In 64-bit mode, the default address size is 64 bits and new features, suchas register extensions, are supported for system and application software.#GP(0)Notation indicating a general-protection exception (#GP) with error code of 0.absoluteSaid of a displacement that references the base of a code segment rather than an instruction pointer.Contrast with relative.biased exponentThe sum of a floating-point value’s exponent and a constant bias for a particular floating-point datatype.
The bias makes the range of the biased exponent always positive, which allows reciprocationwithout overflow.byteEight bits.clearTo write a bit value of 0. Compare set.compatibility modeA submode of long mode. In compatibility mode, the default address size is 32 bits, and legacy 16bit and 32-bit applications run without modification.commitTo irreversibly write, in program order, an instruction’s result to software-visible storage, such as aregister (including flags), the data cache, an internal write buffer, or memory.CPLCurrent privilege level.CR0–CR4A register range, from register CR0 through CR4, inclusive, with the low-order register first.CR0.PE = 1Notation indicating that the PE bit of the CR0 register has a value of 1.directReferencing a memory location whose address is included in the instruction’s syntax as animmediate operand.
The address may be an absolute or relative address. Compare indirect.PrefacexviiAMD64 Technology24594—Rev. 3.13—July 2007dirty dataData held in the processor’s caches or internal buffers that is more recent than the copy held inmain memory.displacementA signed value that is added to the base of a segment (absolute addressing) or an instruction pointer(relative addressing). Same as offset.doublewordTwo words, or four bytes, or 32 bits.double quadwordEight words, or 16 bytes, or 128 bits. Also called octword.DS:rSIThe contents of a memory location whose segment address is in the DS register and whose offsetrelative to that segment is in the rSI register.EFER.LME = 0Notation indicating that the LME bit of the EFER register has a value of 0.effective address sizeThe address size for the current instruction after accounting for the default address size and anyaddress-size override prefix.effective operand sizeThe operand size for the current instruction after accounting for the default operand size and anyoperand-size override prefix.elementSee vector.exceptionAn abnormal condition that occurs as the result of executing an instruction.
The processor’sresponse to an exception depends on the type of the exception. For all exceptions except 128-bitmedia SIMD floating-point exceptions and x87 floating-point exceptions, control is transferred tothe handler (or service routine) for that exception, as defined by the exception’s vector. Forfloating-point exceptions defined by the IEEE 754 standard, there are both masked and unmaskedresponses.
When unmasked, the exception handler is called, and when masked, a default responseis provided instead of calling the handler.FF /0Notation indicating that FF is the first byte of an opcode, and a subopcode in the ModR/M byte hasa value of 0.xviiiPreface24594—Rev. 3.13—July 2007AMD64 TechnologyflushAn often ambiguous term meaning (1) writeback, if modified, and invalidate, as in “flush the cacheline,” or (2) invalidate, as in “flush the pipeline,” or (3) change a value, as in “flush to zero.”GDTGlobal descriptor table.IDTInterrupt descriptor table.IGNIgnore. Field is ignored.indirectReferencing a memory location whose address is in a register or other memory location.
Theaddress may be an absolute or relative address. Compare direct.IRBThe virtual-8086 mode interrupt-redirection bitmap.ISTThe long-mode interrupt-stack table.IVTThe real-address mode interrupt-vector table.LDTLocal descriptor table.legacy x86The legacy x86 architecture. See “Related Documents” on page xxvi for descriptions of the legacyx86 architecture.legacy modeAn operating mode of the AMD64 architecture in which existing 16-bit and 32-bit applications andoperating systems run without modification. A processor implementation of the AMD64architecture can run in either long mode or legacy mode.
Legacy mode has three submodes, realmode, protected mode, and virtual-8086 mode.long modeAn operating mode unique to the AMD64 architecture. A processor implementation of theAMD64 architecture can run in either long mode or legacy mode. Long mode has two submodes,64-bit mode and compatibility mode.lsbLeast-significant bit.PrefacexixAMD64 Technology24594—Rev. 3.13—July 2007LSBLeast-significant byte.main memoryPhysical memory, such as RAM and ROM (but not cache memory) that is installed in a particularcomputer system.mask(1) A control bit that prevents the occurrence of a floating-point exception from invoking anexception-handling routine. (2) A field of bits used for a control purpose.MBZMust be zero.
If software attempts to set an MBZ bit to 1, a general-protection exception (#GP)occurs.memoryUnless otherwise specified, main memory.ModRMA byte following an instruction opcode that specifies address calculation based on mode (Mod),register (R), and memory (M) variables.moffsetA 16, 32, or 64-bit offset that specifies a memory operand directly, without using a ModRM or SIBbyte.msbMost-significant bit.MSBMost-significant byte.multimedia instructionsA combination of 128-bit media instructions and 64-bit media instructions.octwordSame as double quadword.offsetSame as displacement.overflowThe condition in which a floating-point number is larger in magnitude than the largest, finite,positive or negative number that can be represented in the data-type format being used.xxPreface24594—Rev.
3.13—July 2007AMD64 TechnologypackedSee vector.PAEPhysical-address extensions.physical memoryActual memory, consisting of main memory and cache.probeA check for an address in a processor’s caches or internal buffers. External probes originateoutside the processor, and internal probes originate within the processor.protected modeA submode of legacy mode.quadwordFour words, or eight bytes, or 64 bits.RAZRead as zero (0), regardless of what is written.real-address modeSee real mode.real modeA short name for real-address mode, a submode of legacy mode.relativeReferencing with a displacement (also called offset) from an instruction pointer rather than thebase of a code segment.
Contrast with absolute.reservedFields marked as reserved may be used at some future time.To preserve compatibility with future processors, reserved fields require special handling whenread or written by software.Reserved fields may be further qualified as MBZ, RAZ, SBZ or IGN (see definitions).Software must not depend on the state of a reserved field, nor upon the ability of such fields toreturn to a previously written state.If a reserved field is not marked with one of the above qualifiers, software must not change the stateof that field; it must reload that field with the same values returned from a prior read.REXAn instruction prefix that specifies a 64-bit operand size and provides access to additionalregisters.PrefacexxiAMD64 Technology24594—Rev.
3.13—July 2007RIP-relative addressingAddressing relative to the 64-bit RIP instruction pointer.setTo write a bit value of 1. Compare clear.SIBA byte following an instruction opcode that specifies address calculation based on scale (S), index(I), and base (B).SIMDSingle instruction, multiple data. See vector.SSEStreaming SIMD extensions instruction set. See 128-bit media instructions and 64-bit mediainstructions.SSE2Extensions to the SSE instruction set. See 128-bit media instructions and 64-bit mediainstructions.SSE3Further extensions to the SSE instruction set.
See 128-bit media instructions.sticky bitA bit that is set or cleared by hardware and that remains in that state until explicitly changed bysoftware.TOPThe x87 top-of-stack pointer.TPRTask-priority register (CR8).TSSTask-state segment.underflowThe condition in which a floating-point number is smaller in magnitude than the smallest nonzero,positive or negative number that can be represented in the data-type format being used.vector(1) A set of integer or floating-point values, called elements, that are packed into a single operand.Most of the 128-bit and 64-bit media instructions use vectors as operands.
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