Volume 3 General-Purpose and System Instructions (794097), страница 7
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Vectors are also calledpacked or SIMD (single-instruction multiple-data) operands.xxiiPreface24594—Rev. 3.13—July 2007AMD64 Technology(2) An index into an interrupt descriptor table (IDT), used to access exception handlers. Compareexception.virtual-8086 modeA submode of legacy mode.wordTwo bytes, or 16 bits.x86See legacy x86.RegistersIn the following list of registers, the names are used to refer either to a given register or to the contentsof that register:AH–DHThe high 8-bit AH, BH, CH, and DH registers.
Compare AL–DL.AL–DLThe low 8-bit AL, BL, CL, and DL registers. Compare AH–DH.AL–r15BThe low 8-bit AL, BL, CL, DL, SIL, DIL, BPL, SPL, and R8B–R15B registers, available in 64-bitmode.BPBase pointer register.CRnControl register number n.CSCode segment register.eAX–eSPThe 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers. Compare rAX–rSP.EFERExtended features enable register.eFLAGS16-bit or 32-bit flags register.
Compare rFLAGS.PrefacexxiiiAMD64 Technology24594—Rev. 3.13—July 2007EFLAGS32-bit (extended) flags register.eIP16-bit or 32-bit instruction-pointer register. Compare rIP.EIP32-bit (extended) instruction-pointer register.FLAGS16-bit flags register.GDTRGlobal descriptor table register.GPRsGeneral-purpose registers. For the 16-bit data size, these are AX, BX, CX, DX, DI, SI, BP, and SP.For the 32-bit data size, these are EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP. For the 64-bitdata size, these include RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, and R8–R15.IDTRInterrupt descriptor table register.IP16-bit instruction-pointer register.LDTRLocal descriptor table register.MSRModel-specific register.r8–r15The 8-bit R8B–R15B registers, or the 16-bit R8W–R15W registers, or the 32-bit R8D–R15Dregisters, or the 64-bit R8–R15 registers.rAX–rSPThe 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers, or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers, or the 64-bit RAX, RBX, RCX, RDX, RDI, RSI, RBP, and RSPregisters.
Replace the placeholder r with nothing for 16-bit size, “E” for 32-bit size, or “R” for 64bit size.RAX64-bit version of the EAX register.xxivPreface24594—Rev. 3.13—July 2007AMD64 TechnologyRBP64-bit version of the EBP register.RBX64-bit version of the EBX register.RCX64-bit version of the ECX register.RDI64-bit version of the EDI register.RDX64-bit version of the EDX register.rFLAGS16-bit, 32-bit, or 64-bit flags register. Compare RFLAGS.RFLAGS64-bit flags register.
Compare rFLAGS.rIP16-bit, 32-bit, or 64-bit instruction-pointer register. Compare RIP.RIP64-bit instruction-pointer register.RSI64-bit version of the ESI register.RSP64-bit version of the ESP register.SPStack pointer register.SSStack segment register.TPRTask priority register, a new register introduced in the AMD64 architecture to speed interruptmanagement.TRTask register.PrefacexxvAMD64 Technology24594—Rev. 3.13—July 2007Endian OrderThe x86 and AMD64 architectures address memory using little-endian byte-ordering. Multibytevalues are stored with their least-significant byte at the lowest byte address, and they are illustratedwith their least significant byte at the right side.
Strings are illustrated in reverse order, because theaddresses of their bytes increase from right to left.Related Documents•••••••••••••••••••Peter Abel, IBM PC Assembly Language and Programming, Prentice-Hall, Englewood Cliffs, NJ,1995.Rakesh Agarwal, 80x86 Architecture & Programming: Volume II, Prentice-Hall, EnglewoodCliffs, NJ, 1991.AMD, AMD-K6™ MMX™ Enhanced Processor Multimedia Technology, Sunnyvale, CA, 2000.AMD, 3DNow!™ Technology Manual, Sunnyvale, CA, 2000.AMD, AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets, Sunnyvale, CA, 2000.Don Anderson and Tom Shanley, Pentium Processor System Architecture, Addison-Wesley, NewYork, 1995.Nabajyoti Barkakati and Randall Hyde, Microsoft Macro Assembler Bible, Sams, Carmel, Indiana,1992.Barry B.
Brey, 8086/8088, 80286, 80386, and 80486 Assembly Language Programming,Macmillan Publishing Co., New York, 1994.Barry B. Brey, Programming the 80286, 80386, 80486, and Pentium Based Personal Computer,Prentice-Hall, Englewood Cliffs, NJ, 1995.Ralf Brown and Jim Kyle, PC Interrupts, Addison-Wesley, New York, 1994.Penn Brumm and Don Brumm, 80386/80486 Assembly Language Programming, WindcrestMcGraw-Hill, 1993.Geoff Chappell, DOS Internals, Addison-Wesley, New York, 1994.Chips and Technologies, Inc. Super386 DX Programmer’s Reference Manual, Chips andTechnologies, Inc., San Jose, 1992.John Crawford and Patrick Gelsinger, Programming the 80386, Sybex, San Francisco, 1987.Cyrix Corporation, 5x86 Processor BIOS Writer's Guide, Cyrix Corporation, Richardson, TX,1995.Cyrix Corporation, M1 Processor Data Book, Cyrix Corporation, Richardson, TX, 1996.Cyrix Corporation, MX Processor MMX Extension Opcode Table, Cyrix Corporation, Richardson,TX, 1996.Cyrix Corporation, MX Processor Data Book, Cyrix Corporation, Richardson, TX, 1997.Ray Duncan, Extending DOS: A Programmer's Guide to Protected-Mode DOS, Addison Wesley,NY, 1991.xxviPreface24594—Rev.
3.13—July 2007••••••••••••••••••••••AMD64 TechnologyWilliam B. Giles, Assembly Language Programming for the Intel 80xxx Family, Macmillan, NewYork, 1991.Frank van Gilluwe, The Undocumented PC, Addison-Wesley, New York, 1994.John L. Hennessy and David A. Patterson, Computer Architecture, Morgan Kaufmann Publishers,San Mateo, CA, 1996.Thom Hogan, The Programmer’s PC Sourcebook, Microsoft Press, Redmond, WA, 1991.Hal Katircioglu, Inside the 486, Pentium, and Pentium Pro, Peer-to-Peer Communications, MenloPark, CA, 1997.IBM Corporation, 486SLC Microprocessor Data Sheet, IBM Corporation, Essex Junction, VT,1993.IBM Corporation, 486SLC2 Microprocessor Data Sheet, IBM Corporation, Essex Junction, VT,1993.IBM Corporation, 80486DX2 Processor Floating Point Instructions, IBM Corporation, EssexJunction, VT, 1995.IBM Corporation, 80486DX2 Processor BIOS Writer's Guide, IBM Corporation, Essex Junction,VT, 1995.IBM Corporation, Blue Lightning 486DX2 Data Book, IBM Corporation, Essex Junction, VT,1994.Institute of Electrical and Electronics Engineers, IEEE Standard for Binary Floating-PointArithmetic, ANSI/IEEE Std 754-1985.Institute of Electrical and Electronics Engineers, IEEE Standard for Radix-Independent FloatingPoint Arithmetic, ANSI/IEEE Std 854-1987.Muhammad Ali Mazidi and Janice Gillispie Mazidi, 80X86 IBM PC and Compatible Computers,Prentice-Hall, Englewood Cliffs, NJ, 1997.Hans-Peter Messmer, The Indispensable Pentium Book, Addison-Wesley, New York, 1995.Karen Miller, An Assembly Language Introduction to Computer Architecture: Using the IntelPentium, Oxford University Press, New York, 1999.Stephen Morse, Eric Isaacson, and Douglas Albert, The 80386/387 Architecture, John Wiley &Sons, New York, 1987.NexGen Inc., Nx586 Processor Data Book, NexGen Inc., Milpitas, CA, 1993.NexGen Inc., Nx686 Processor Data Book, NexGen Inc., Milpitas, CA, 1994.Bipin Patwardhan, Introduction to the Streaming SIMD Extensions in the Pentium III,www.x86.org/articles/sse_pt1/ simd1.htm, June, 2000.Peter Norton, Peter Aitken, and Richard Wilton, PC Programmer’s Bible, Microsoft Press,Redmond, WA, 1993.PharLap 386|ASM Reference Manual, Pharlap, Cambridge MA, 1993.PharLap TNT DOS-Extender Reference Manual, Pharlap, Cambridge MA, 1995.PrefacexxviiAMD64 Technology•••••••24594—Rev.
3.13—July 2007Sen-Cuo Ro and Sheau-Chuen Her, i386/i486 Advanced Programming, Van Nostrand Reinhold,New York, 1993.Jeffrey P. Royer, Introduction to Protected Mode Programming, course materials for an onsiteclass, 1992.Tom Shanley, Protected Mode System Architecture, Addison Wesley, NY, 1996.SGS-Thomson Corporation, 80486DX Processor SMM Programming Manual, SGS-ThomsonCorporation, 1995.Walter A. Triebel, The 80386DX Microprocessor, Prentice-Hall, Englewood Cliffs, NJ, 1992.John Wharton, The Complete x86, MicroDesign Resources, Sebastopol, California, 1994.Web sites and newsgroups:- www.amd.com- news.comp.arch- news.comp.lang.asm.x86- news.intel.microprocessors- news.microsoftxxviiiPreface24594—Rev. 3.13—July 20071AMD64 TechnologyInstruction FormatsThe format of an instruction encodes its operation, as well as the locations of the instruction’s initialoperands and the result of the operation.
This section describes the general format and parameters usedby all instructions. For information on the specific format(s) for each instruction, see:•••••Chapter 3, “General-Purpose Instruction Reference.”Chapter 4, “System Instruction Reference.”“128-Bit Media Instruction Reference” in Volume 4.“64-Bit Media Instruction Reference” in Volume 5.“x87 Floating-Point Instruction Reference” in Volume 5.1.1Instruction Byte OrderAn instruction can be between one and 15 bytes in length. Figure 1-1 shows the byte order of theinstruction format.LegacyPrefixREXPrefixOpcode(1 or 2 bytes)ModRMSIBDisplacementImmediate(1, 2, 4, or 8 bytes) (1, 2, 4, or 8 bytes)Instruction Length ≤ 15 BytesFigure 1-1.
Instruction Byte-OrderInstructions are stored in memory in little-endian order. The least-significant byte of an instruction isstored at its lowest memory address, as shown in Figure 1-2 on page 2.Instruction Formats1AMD64 Technology24594—Rev. 3.13—July 20077Most-signifcant(highest) address£ 15 BytesLeast-signifcant(lowest) address0ImmediateImmediateImmediateImmediateDisplacementDisplacementDisplacementDisplacementSIBModRMOpcodeOpcodeREX PrefixLegacy PrefixLegacy PrefixLegacy PrefixLegacy Prefix***********(all two-byte opcodes have 0Fh as their first byte)+ (available only in 64-bit mode)+++* optional, depending on the instruction++ optional, with most instructions513-304.epsFigure 1-2.Little-Endian Byte-Order of Instruction Stored in MemoryThe basic operation of an instruction is specified by an opcode.
The opcode is one or two bytes long, asdescribed in “Opcode” on page 17. An opcode can be preceded by any number of legacy prefixes.These prefixes can be classified as belonging to any of the five groups of prefixes described in“Instruction Prefixes” on page 3. The legacy prefixes modify an instruction’s default address size,operand size, or segment, or they invoke a special function such as modification of the opcode, atomicbus-locking, or repetition. The REX prefix can be used in 64-bit mode to access the register extensionsillustrated in “Application-Programming Register Set” in Volume 1.
If a REX prefix is used, it mustimmediately precede the first opcode byte.An instruction’s opcode consists of one or two bytes. In several 128-bit and 64-bit media instructions,a legacy operand-size or repeat prefix byte is used in a special-purpose way to modify the opcode. Theopcode can be followed by a mode-register-memory (ModRM) byte, which further describes theoperation and/or operands. The opcode, or the opcode and ModRM byte, can also be followed by ascale-index-base (SIB) byte, which describes the scale, index, and base forms of memory addressing.The ModRM and SIB bytes are described in “ModRM and SIB Bytes” on page 17, but their legacyfunctions can be modified by the REX prefix (“Instruction Prefixes” on page 3).The 15-byte instruction-length limit can only be exceeded by using redundant prefixes.
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