Volume 3 General-Purpose and System Instructions (794097), страница 9
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By default, theyreference both the DS and ES segments (DS:rSI and ES:rDI). These instructions can override theirDS-segment reference, as shown in Table 1-5, but they cannot override their ES-segmentreference.Instructions that Reference the Stack Segment—If an instruction’s encoding references the rBP orrSP base register, the default segment is the stack segment (SS).
All instructions that reference thestack (push, pop, call, interrupt, return from interrupt) use SS by default. These instructions cannotuse the segment-override prefix.Table 1-5. Segment-Override PrefixesMnemonicPrefix Byte(Hex)CS12EForces use of current CS segment for memory operands.DS13EForces use of current DS segment for memory operands.126Forces use of current ES segment for memory operands.FS64Forces use of current FS segment for memory operands.GS65Forces use of current GS segment for memory operands.SS136Forces use of current SS segment for memory operands.ESDescriptionNote:1. In 64-bit mode, the CS, DS, ES, and SS segment overrides are ignored.Segment Overrides in 64-Bit Mode.
In 64-bit mode, the CS, DS, ES, and SS segment-overrideprefixes have no effect. These four prefixes are not treated as segment-override prefixes for thepurposes of multiple-prefix rules. Instead, they are treated as null prefixes.The FS and GS segment-override prefixes are treated as true segment-override prefixes in 64-bit mode.Use of the FS or GS prefix causes their respective segment bases to be added to the effective addresscalculation. See “FS and GS Registers in 64-Bit Mode” in Volume 2 for details.1.2.5 Lock PrefixThe LOCK prefix causes certain kinds of memory read-modify-write instructions to occur atomically.The mechanism for doing so is implementation-dependent (for example, the mechanism may involve8Instruction Formats24594—Rev.
3.13—July 2007AMD64 Technologybus signaling or packet messaging between the processor and a memory controller). The prefix isintended to give the processor exclusive use of shared memory in a multiprocessor system.The LOCK prefix can only be used with forms of the following instructions that write a memoryoperand: ADC, ADD, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, CMPXCHG16B, DEC,INC, NEG, NOT, OR, SBB, SUB, XADD, XCHG, and XOR.
An invalid-opcode exception occurs ifthe LOCK prefix is used with any other instruction.1.2.6 Repeat PrefixesThe repeat prefixes cause repetition of certain instructions that load, store, move, input, or outputstrings. The prefixes should only be used with such string instructions. Two pairs of repeat prefixes,REPE/REPZ and REPNE/REPNZ, perform the same repeat functions for certain compare-string andscan-string instructions. The repeat function uses rCX as a count register. The size of rCX is based onaddress size, as shown in Table 1-4 on page 7.REP.
The REP prefix repeats its associated string instruction the number of times specified in thecounter register (rCX). It terminates the repetition when the value in rCX reaches 0. The prefix can beused with the INS, LODS, MOVS, OUTS, and STOS instructions. Table 1-6 shows the valid REPprefix opcodes.Table 1-6.REP Prefix OpcodesMnemonicOpcodeREP INS reg/mem8, DXREP INSBF3 6CREP INS reg/mem16/32, DXREP INSWREP INSDF3 6DREP LODS mem8REP LODSBF3 ACREP LODS mem16/32/64REP LODSWREP LODSDREP LODSQF3 ADREP MOVS mem8, mem8REP MOVSBF3 A4REP MOVS mem16/32/64, mem16/32/64REP MOVSWREP MOVSDREP MOVSQF3 A5REP OUTS DX, reg/mem8REP OUTSBF3 6EInstruction Formats9AMD64 Technology24594—Rev.
3.13—July 2007Table 1-6.REP Prefix Opcodes (continued)MnemonicOpcodeREP OUTS DX, reg/mem16/32REP OUTSWREP OUTSDF3 6FREP STOS mem8REP STOSBF3 AAREP STOS mem16/32/64REP STOSWREP STOSDREP STOSQF3 ABREPE and REPZ. REPE and REPZ are synonyms and have identical opcodes. These prefixes repeattheir associated string instruction the number of times specified in the counter register (rCX). Therepetition terminates when the value in rCX reaches 0 or when the zero flag (ZF) is cleared to 0. TheREPE and REPZ prefixes can be used with the CMPS, CMPSB, CMPSD, CMPSW, SCAS, SCASB,SCASD, and SCASW instructions.
Table 1-7 shows the valid REPE and REPZ prefix opcodes.Table 1-7.REPE and REPZ Prefix OpcodesMnemonicOpcodeREPx CMPS mem8, mem8REPx CMPSBF3 A6REPx CMPS mem16/32/64, mem16/32/64REPx CMPSWREPx CMPSDREPx CMPSQF3 A7REPx SCAS mem8REPx SCASBF3 AEREPx SCAS mem16/32/64REPx SCASWREPx SCASDREPx SCASQF3 AFREPNE and REPNZ. REPNE and REPNZ are synonyms and have identical opcodes.
These prefixesrepeat their associated string instruction the number of times specified in the counter register (rCX).The repetition terminates when the value in rCX reaches 0 or when the zero flag (ZF) is set to 1. TheREPNE and REPNZ prefixes can be used with the CMPS, CMPSB, CMPSD, CMPSW, SCAS,SCASB, SCASD, and SCASW instructions. Table 1-8 on page 11 shows the valid REPNE andREPNZ prefix opcodes.10Instruction Formats24594—Rev.
3.13—July 2007Table 1-8.AMD64 TechnologyREPNE and REPNZ Prefix OpcodesMnemonicOpcodeREPNx CMPS mem8, mem8REPNx CMPSBF2 A6REPNx CMPS mem16/32/64, mem16/32/64REPNx CMPSWREPNx CMPSDREPNx CMPSQF2 A7REPNx SCAS mem8REPNx SCASBF2 AEREPNx SCAS mem16/32/64REPNx SCASWREPNx SCASDREPNx SCASQF2 AFInstructions that Cannot Use Repeat Prefixes.
In general, the repeat prefixes should only be usedin the string instructions listed in tables 1-6, 1-7, and 1-8, and in 128-bit or 64-bit media instructions.When used in media instructions, the F2h and F3h prefixes act in a special way to modify the opcoderather than cause a repeat operation. The result of using a 66h operand-size prefix along with an F2h orF3h prefix in 128-bit or 64-bit media instructions is unpredictable.Optimization of Repeats. Depending on the hardware implementation, the repeat prefixes can have asetup overhead.
If the repeated count is variable, the overhead can sometimes be avoided by substitutinga simple loop to move or store the data. Repeated string instructions can be expanded into equivalentsequences of inline loads and stores or a sequence of stores can be used to emulate a REP STOS.For repeated string moves, performance can be maximized by moving the largest possible operandsize. For example, use REP MOVSD rather than REP MOVSW and REP MOVSW rather than REPMOVSB. Use REP STOSD rather than REP STOSW and REP STOSW rather than REP MOVSB.Depending on the hardware implementation, string moves with the direction flag (DF) cleared to 0(up) may be faster than string moves with DF set to 1 (down).
DF = 1 is only needed for certain casesof overlapping REP MOVS, such as when the source and the destination overlap.1.2.7 REX PrefixesREX prefixes are a group of instruction-prefix bytes that can be used only in 64-bit mode. They enableaccess to the AMD64 register extensions. Figure 1-1 on page 1 and Figure 1-2 on page 2 show how aREX prefix fits within the byte order of instructions. REX prefixes enable the following features in 64bit mode:••Use of the extended GPR (Figure 2-3 on page 25) or XMM registers (Figure 2-8 on page 30).Use of the 64-bit operand size when accessing GPRs.Instruction Formats11AMD64 Technology••24594—Rev.
3.13—July 2007Use of the extended control and debug registers, as described in “64-Bit-Mode Extended ControlRegisters” in Volume 2 and “64-Bit-Mode Extended Debug Registers” in Volume 2.Use of the uniform byte registers (AL–R15).Table 1-9 shows the REX prefixes. The value of a REX prefix is in the range 40h through 4Fh,depending on the particular combination of AMD64 register extensions desired.Table 1-9. REX Instruction PrefixesPrefix TypeMnemonicREX.WRegister ExtensionsREX.RREX.XPrefix Code(Hex)401through4F1DescriptionAccess an AMD64 registerextension.REX.BNote:1.
See Table 1-11 for encoding of REX prefixes.A REX prefix is normally required with an instruction that accesses a 64-bit GPR or one of theextended GPR or XMM registers. Only a few instructions have an operand size that defaults to (or isfixed at) 64 bits in 64-bit mode, and thus do not need a REX prefix. These exceptions to the normalrule are listed in Table 1-10.Table 1-10.Instructions Not Requiring REX Size Prefix in 64-Bit ModeCALL (Near)POP reg/memENTERPOP regJccPOP FSJrCXZPOP GSJMP (Near)POPFQLEAVEPUSH imm8LGDTPUSH imm32LIDTPUSH reg/memLLDTPUSH regLOOPPUSH FSLOOPccPUSH GSLTRPUSHFQMOV CR(n)RET (Near)MOV DR(n)An instruction can have only one REX prefix, although the prefix can express several extensionfeatures.
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