Volume 3 General-Purpose and System Instructions (794097), страница 10
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If a REX prefix is used, it must immediately precede the first opcode byte in the instructionformat. Any other placement of a REX prefix, or any use of a REX prefix in an instruction that does12Instruction Formats24594—Rev. 3.13—July 2007AMD64 Technologynot access an extended register, is ignored. The legacy instruction-size limit of 15 bytes still applies toinstructions that contain a REX prefix.REX prefixes are a set of sixteen values that span one row of the main opcode map and occupy entries40h through 4Fh.
Table 1-11 and Figure 1-3 on page 15 show the prefix fields and their uses.Table 1-11. REX Prefix-Byte FieldsMnemonicBit Position—7–4REX.W30 = Default operand size1 = 64-bit operand sizeREX.R21-bit (high) extension of the ModRM regfield1, thus permitting access to 16registers.REX.X11-bit (high) extension of the SIB index field1,thus permitting access to 16 registers.01-bit (high) extension of the ModRM r/mfield1, SIB base field1, or opcode reg field,thus permitting access to 16 registers.REX.BDefinition0100Note:1. For a description of the ModRM and SIB bytes, see “ModRM and SIB Bytes” onpage 17.REX.W: Operand Width.
Setting the REX.W bit to 1 specifies a 64-bit operand size. Like theexisting 66h operand-size prefix, the REX 64-bit operand-size override has no effect on byteoperations. For non-byte operations, the REX operand-size override takes precedence over the 66hprefix. If a 66h prefix is used together with a REX prefix that has the REX.W bit set to 1, the 66hprefix is ignored. However, if a 66h prefix is used together with a REX prefix that has the REX.W bitcleared to 0, the 66h prefix is not ignored and the operand size becomes 16 bits.REX.R: Register.
The REX.R bit adds a 1-bit (high) extension to the ModRM reg field (page 17)when that field encodes a GPR, XMM, control, or debug register. REX.R does not modify ModRM regwhen that field specifies other registers or opcodes. REX.R is ignored in such cases.REX.X: Index. The REX.X bit adds a 1-bit (high) extension to the SIB index field (page 17).REX.B: Base. The REX.B bit either adds a 1-bit (high) extension to the base in the ModRM r/m fieldor SIB base field, or it adds a 1-bit (high) extension to the opcode reg field used for accessing GPRs.(See Table 2-2 on page 40 for more about the REX.B bit.)Encoding Examples.
Figure 1-3 on page 15 shows four examples of how the R, X, and B bits ofREX prefixes are concatenated with fields from the ModRM byte, SIB byte, and opcode to specifyregister and memory addressing. The R, X, and B bits are described in Table 1-11 on page 13.Instruction Formats13AMD64 Technology24594—Rev. 3.13—July 2007Byte-Register Addressing. In the legacy architecture, the byte registers (AH, AL, BH, BL, CH, CL,DH, and DL, shown in Figure 2-2 on page 24) are encoded in the ModRM reg or r/m field or in theopcode reg field as registers 0 through 7. The REX prefix provides an additional byte-registeraddressing capability that makes the least-significant byte of any GPR available for byte operations(Figure 2-3 on page 25).
This provides a uniform set of byte, word, doubleword, and quadwordregisters better suited for register allocation by compilers.Special Encodings for Registers. Readers who need to know the details of instruction encodingsshould be aware that certain combinations of the ModRM and SIB fields have special meaning forregister encodings. For some of these combinations, the instruction fields expanded by the REX prefixare not decoded (treated as don’t cares), thereby creating aliases of these encodings in the extendedregisters. Table 1-12 on page 16 describes how each of these cases behaves.Implications for INC and DEC Instructions. The REX prefix values are taken from the 16 single-byte INC and DEC instructions, one for each of the eight GPRs.
Therefore, these single-byte opcodesfor INC and DEC are not available in 64-bit mode, although they are available in legacy andcompatibility modes. The functionality of these INC and DEC instructions is still available in 64-bitmode, however, using the ModRM forms of those instructions (opcodes FF /0 and FF /1).14Instruction Formats24594—Rev. 3.13—July 2007AMD64 TechnologyCase 1: Register-Register Addressing (No Memory Operand)REX Prefix4WRXBModRM Bytemod reg r/m11 rrr bbbOpcodeREX.X is not used44Rrrr BbbbCase 2: Memory Addressing Without an SIB ByteREX Prefix4WRXBModRM Bytemod reg r/m!11 rrr bbbOpcodeREX.X is not usedModRM reg field != 10044Rrrr BbbbCase 3: Memory Addressing With an SIB ByteREX Prefix4WRXBModRM Bytemod reg r/m!11 rrr 100OpcodeSIB Bytescale index basebb xxx bbb444RrrrXxxx BbbbCase 4: Register Operand Coded in Opcode ByteREX Prefix4WRXBOpcode ByteopregbbbREX.R is not usedREX.X is not used4Bbbb513-302.epsFigure 1-3.
Encoding Examples of REX-Prefix R, X, and B BitsInstruction Formats15AMD64 Technology24594—Rev. 3.13—July 2007Table 1-12. Special REX Encodings for RegistersModRM and SIBEncodings2Meaning in Legacy andCompatibility ModesImplications in Legacyand CompatibilityModesModRM Byte:• mod ≠ 11SIB byte is present.• r/m1 = 100 (ESP)ModRM Byte:• mod = 00• r/m1 = x101 (EBP)Using EBP without adisplacement must bedone by setting mod = 01Base register is not used.with a displacement of 0(with or without an indexregister).• index = x100 (ESP)REX prefix adds a fourthbit (x), which is notdecoded (don’t care).Therefore, using RBP orR13 without adisplacement must bedone via mod = 01 with adisplacement of 0.Index register is not used.ESP cannot be used asan index register.Base register is not usedif ModRM.mod = 00.Base register depends onmod encoding.
UsingEBP with a scaled indexand without adisplacement must bedone by setting mod = 01with a displacement of 0.REX prefix adds a fourthbit (b), which is notdecoded (don’t care).Therefore, using RBP orR13 without adisplacement must bedone via mod = 01 with adisplacement of 0 (with orwithout an index register).SIB Byte:• base = b101 (EBP)• ModRM.mod = 00REX prefix adds a fourthbit (b), which is decodedand modifies the baseregister in the SIB byte.Therefore, the SIB byte isalso required for R12based addressing.REX prefix adds a fourthbit (x), which is decoded.Therefore, there are noadditional implications.The expanded index fieldis used to distinguish RSPfrom R12, allowing R12 tobe used as an index.SIB Byte:1SIB byte is required forESP-based addressing.Additional REXImplicationsNote:1.
The REX-prefix bit is shown in the fourth (most-significant) bit position of the encodings for the ModRM r/m, SIBindex, and SIB base fields. The lower-case “x” for ModRM r/m (rather than the upper-case “B” shown in Figure 1-3on page 15) indicates that the REX-prefix bit is not decoded (don’t care).2. For a description of the ModRM and SIB bytes, see “ModRM and SIB Bytes” on page 17.16Instruction Formats24594—Rev.
3.13—July 20071.3AMD64 TechnologyOpcodeEach instruction has a unique opcode, although assemblers can support multiple mnemonics for asingle instruction opcode. The opcode specifies the operation that the instruction performs and, incertain cases, the kinds of operands it uses. An opcode consists of one or two bytes, but certain 128-bitmedia instructions also use a prefix byte in a special way to modify the opcode.
The 3-bit reg field ofthe ModRM byte (“ModRM and SIB Bytes” on page 17) is also used in certain instructions either forthree additional opcode bits or for a register specification.128-Bit and 64-Bit Media Instruction Opcodes. Many 128-bit and 64-bit media instructionsinclude a 66h, F2h, or F3h prefix byte in a special way to modify the opcode.
These same byte valuescan be used in certain general-purpose and x87 instructions to modify operand size (66h) or repeat theoperation (F2h, F3h). In 128-bit and 64-bit media instructions, however, such prefix bytes modify theopcode. If a 128-bit or 64-bit media instruction uses one of these three prefixes, and also includes anyother prefix in the 66h, F2h, and F3h group, the result is unpredictable.All opcodes for 64-bit media instructions begin with a 0Fh byte.
In the case of 64-bit floating-point(3DNow!) instructions, the 0Fh byte is followed by a second 0Fh opcode byte. A third opcode byteoccupies the same position at the end of a 3DNow! instruction as would an immediate byte. The valueof the immediate byte is shown as the third opcode byte-value in the syntax for each instruction in“64-Bit Media Instruction Reference” in Volume 5. The format is:0Fh 0Fh ModRM [SIB] [displacement] 3DNow!_third_opcode_byteFor details on opcode encoding, see Appendix A, “Opcode and Operand Encodings.”1.4ModRM and SIB BytesThe ModRM byte is used in certain instruction encodings to:•••Define a register reference.Define a memory reference.Provide additional opcode bits with which to define the instruction’s function.ModRM bytes have three fields—mod, reg, and r/m.
The reg field provides additional opcode bits withwhich to define the function of the instruction or one of its operands. The mod and r/m fields are usedtogether with each other and, in 64-bit mode, with the REX.R and REX.B bits of the REX prefix(page 11), to specify the location of an instruction’s operands and certain of the possible addressingmodes (specifically, the non-complex modes).Figure 1-4 on page 18 shows the format of a ModRM byte.Instruction Formats17AMD64 Technology24594—Rev.
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