Volume 3 General-Purpose and System Instructions (794097), страница 5
Текст из файла (страница 5)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 3-1.MOVD Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160Figure A-1.ModRM-Byte Fields . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348Figure A-2.ModRM-Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 363Figure A-3.SIB Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369Figure D-1.Instruction Subsets vs. CPUID Feature Sets. . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 406FiguresixAMD64 Technologyx24594—Rev. 3.13—July 2007Figures24594—Rev. 3.12—July 2007AMD64 TechnologyTablesTable 1-1.Legacy Instruction Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Table 1-2.Operand-Size Overrides . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Table 1-3.Address-Size Overrides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Table 1-4.Pointer and Count Registers and the Address-Size Prefix .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 1-5.Segment-Override Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 1-6.REP Prefix Opcodes . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 1-7.REPE and REPZ Prefix Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 1-8.REPNE and REPNZ Prefix Opcodes . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 1-9.REX Instruction Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 1-10.Instructions Not Requiring REX Size Prefix in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . .
. . . . 12Table 1-11.REX Prefix-Byte Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 1-12.Special REX Encodings for Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 1-13.Encoding for RIP-Relative Addressing. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 2-1.Interrupt-Vector Source and Cause. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 2-2.+rb, +rw, +rd, and +rq Register Value . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 40Table 3-1.Instruction Support Indicated by CPUID Feature Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 3-2.Processor Vendor Return Values . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Table 3-3.Locality References for the Prefetch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Table A-1.One-Byte Opcodes, Low Nibble 0–7h .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341Table A-2.One-Byte Opcodes, Low Nibble 8–Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342Table A-3.Second Byte of Two-Byte Opcodes, Low Nibble 0–7h . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 343Table A-4.Second Byte of Two-Byte Opcodes, Low Nibble 8–Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345Table A-5.rFLAGS Condition Codes for CMOVcc, Jcc, and SETcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348Table A-6.One-Byte and Two-Byte Opcode ModRM Extensions . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 349Table A-7.Opcode 0F 01 and 0F AE ModRM Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351Table A-8.Immediate Byte for 3DNow!™ Opcodes, Low Nibble 0–7h . . . . . . . . . . . . . . . . . . . . . . . . . . 352Table A-9.Immediate Byte for 3DNow!™ Opcodes, Low Nibble 8–Fh . . . . . . .
. . . . . . . . . . . . . . . . . . . 353Table A-10. x87 Opcodes and ModRM Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355Table A-11. rFLAGS Condition Codes for FCMOVcc . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 363Table A-12. ModRM Register References, 16-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364Table A-13. ModRM Memory References, 16-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 364Table A-14. ModRM Register References, 32-Bit and 64-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . 366Table A-15. ModRM Memory References, 32-Bit and 64-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . 367Table A-16. SIB base Field References . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369TablesxiAMD64 Technology24594—Rev. 3.12—July 2007Table A-17. SIB Memory References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 370Table B-1.Operations and Operands in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374Table B-2.Invalid Instructions in 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 399Table B-3.Reassigned Instructions in 64-Bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400Table B-4.Invalid Instructions in Long Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 400Table B-5.Instructions Defaulting to 64-Bit Operand Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400Table C-1.Differences Between Long Mode and Legacy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403Table D-1.Instruction Subsets and CPUID Feature Sets . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409Table E-1.Instruction Effects on RFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435xiiTables24594—Rev. 3.13—July 2007AMD64 TechnologyRevision HistoryDateRevisionDescriptionJuly 20073.13Added the following instructions: “LZCNT” on page 153, “POPCNT”on page 188, “MONITOR” on page 284, and “MWAIT” on page 290.Reformatted information on instruction support indicated by CPUIDfeature bits into Table 3-1.Added minor clarifications and corrected typographical andformatting errors.September20063.12Added minor clarifications and corrected typographical andformatting errors.December20053.11Added SVM instructions; added PAUSE instructions; made factualchanges.January20053.10Clarified CPUID information in exception tables on instruction pages.Added information under “CPUID” on page 103.
Made numeroussmall corrections.3.09Corrected table of valid descriptor types for LAR and LSL instructionsand made several minor formatting, stylistic and factual corrections.Clarified several technical definitions.3.08Corrected description of the operation of flags for RCL, RCR, ROL,and ROR instructions. Clarified description of the MOVSXD andIMUL instructions. Corrected operand specification for the STOSinstruction. Corrected opcode of SETcc, Jcc, instructions. Addedthermal control and thermal monitoring bits to CPUID instruction.Corrected exception tables for POPF, SFENCE, SUB, XLAT, IRET,LSL, MOV(CRn), SGDT/SIDT, SMSW, and STI instructions.Corrected many small typos and incorporated branding terminology.September2003April 2003Revision HistoryxiiiAMD64 Technologyxiv24594—Rev.
3.13—July 2007Revision History24594—Rev. 3.13—July 2007AMD64 TechnologyPrefaceAbout This BookThis book is part of a multivolume work entitled the AMD64 Architecture Programmer’s Manual. Thistable lists each volume and its order number.TitleOrder No.Volume 1: Application Programming24592Volume 2: System Programming24593Volume 3: General-Purpose and System Instructions24594Volume 4: 128-Bit Media Instructions26568Volume 5: 64-Bit Media and x87 Floating-Point Instructions26569AudienceThis volume (Volume 3) is intended for all programmers writing application or system software for aprocessor that implements the AMD64 architecture. Descriptions of general-purpose instructionsassume an understanding of the application-level programming topics described in Volume 1.Descriptions of system instructions assume an understanding of the system-level programming topicsdescribed in Volume 2.Contact InformationTo submit questions or comments concerning this document, contact our technical documentation staffat AMD64.Feedback@amd.com.OrganizationVolumes 3, 4, and 5 describe the AMD64 architecture’s instruction set in detail.
Together, they covereach instruction’s mnemonic syntax, opcodes, functions, affected flags, and possible exceptions.The AMD64 instruction set is divided into five subsets:••••General-purpose instructionsSystem instructions128-bit media instructions64-bit media instructionsPrefacexvAMD64 Technology24594—Rev. 3.13—July 2007x87 floating-point instructions•Several instructions belong to—and are described identically in—multiple instruction subsets.This volume describes the general-purpose and system instructions. The index at the end crossreferences topics within this volume.
For other topics relating to the AMD64 architecture, and forinformation on instructions in other subsets, see the tables of contents and indexes of the othervolumes.DefinitionsMany of the following definitions assume an in-depth knowledge of the legacy x86 architecture. See“Related Documents” on page xxvi for descriptions of the legacy x86 architecture.Terms and NotationIn addition to the notation described below, “Opcode-Syntax Notation” on page 339 describes notationrelating specifically to opcodes.1011bA binary value—in this example, a 4-bit value.F0EAhA hexadecimal value—in this example a 2-byte value.[1,2)A range that includes the left-most value (in this case, 1) but excludes the right-most value (in thiscase, 2).7–4A bit range, from bit 7 to 4, inclusive.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
