Volume 3 General-Purpose and System Instructions (794097), страница 12
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Related instructions are listed below this, followed by a table showing the flagsthat the instruction can affect. Finally, each instruction has a summary of the possible exceptions thatcan occur when executing the instruction. The columns labeled “Real” and “Virtual-8086” apply onlyto execution in legacy mode. The column labeled “Protected” applies both to legacy mode and longmode, because long mode is a superset of legacy protected mode.The 128-bit and 64-bit media instructions also have diagrams illustrating the operation. A fewinstructions have examples or pseudocode describing the action.22Instruction Overview24594—Rev.
3.13—July 2007AMD64 TechnologyMnemonic and any operandsOpcodeDescription of operation24594 Rev. 3.07 September 2003AAMAMD64 TechnologyASCII Adjust After MultiplyConverts the value in the AL register from binary to two unpacked BCD digits in theAH (most significant) and AL (least significant) registers using the following formula:AH = (AL/10d)AL = (AL mod 10d).In most modern assemblers, the AAM instruction adjusts to base-10 values. However,by coding the instruction directly in binary, it can adjust to any base specified by theimmediate byte value (ib) suffixed onto the D4h opcode.
For example, code D408h foroctal, D40Ah for decimal, and D40Ch for duodecimal (base 12).Using this instruction in 64-bit mode generates an invalid-opcode exception.MnemonicOpcodeDescriptionAAMD4 0ACreate a pair of unpacked BCD values in AH and AL.(Invalid in 64-bit mode.)(None)D4 ibCreate a pair of unpacked values to the immediate byte base.(Invalid in 64-bit mode.)“M” means the flag is either set orcleared, depending on the result.Related InstructionsAAA, AAD, AASrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFMMUMU76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M. Unaffected flags are blank. Undefined flags are U.ExceptionsExceptionDivide by zero, #DEVirtualReal 8086 ProtectedXInvalid opcode, #UDXCause of ExceptionX8-bit immediate value was 0.XThis instruction was executed in 64-bit mode.AAMPossible exceptionsand causes, by mode ofoperation“Protected” columncovers both legacyand long modeFigure 2-1.Instruction Overview63Alphabetic mnemonic locatorFormat of Instruction-Detail Pages23AMD64 Technology2.324594—Rev.
3.13—July 2007Summary of Registers and Data TypesThis section summarizes the registers available to software using the five instruction subsets describedin “Instruction Subsets” on page 21. For details on the organization and use of these registers, see theirrespective chapters in volumes 1 and 2.2.3.1 General-Purpose InstructionsRegisters. The size and number of general-purpose registers (GPRs) depends on the operating mode,as do the size of the flags and instruction-pointer registers.
Figure 2-2 shows the registers available inlegacy and compatibility modes.registerencodinghigh8-bitlow8-bit16-bit32-bit0AH (4)ALAXEAX3BH (7)BLBXEBX1CH (5)CLCXECX2DH (6)DLDXEDX6SISIESI7DIDIEDI5BPBPEBP4SPSPESP3116 150FLAGSFLAGS EFLAGSIP31IPEIP0513-311.epsFigure 2-2.General Registers in Legacy and Compatibility ModesFigure 2-3 on page 25 shows the registers accessible in 64-bit mode. Compared with legacy mode,registers become 64 bits wide, eight new data registers (R8–R15) are added and the low byte of all 16GPRs is available for byte operations, and the four high-byte registers of legacy mode (AH, BH, CH,and DH) are not available if the REX prefix is used. The high 32 bits of doubleword operands are zeroextended to 64 bits, but the high bits of word and byte operands are not modified by operations in 64-24Instruction Overview24594—Rev. 3.13—July 2007AMD64 Technologybit mode.
The RFLAGS register is 64 bits wide, but the high 32 bits are reserved. They can be writtenwith anything but they read as zeros (RAZ).not modified for 8-bit operandsnot modified for 16-bit operandszero-extendedfor 32-bit operandsregisterencodinglow8-bit16-bit32-bit64-bit0AH*ALAXEAXRAX3BH*BLBXEBXRBX1CH*CLCXECXRCX2DH*DLDXEDXRDX6SIL**SIESIRSI7DIL**DIEDIRDI5BPL**BPEBPRBP4SPL**SPESPRSP8R8BR8WR8DR89R9BR9WR9DR910R10BR10WR10DR1011R11BR11WR11DR1112R12BR12WR12DR1213R13BR13WR13DR1314R14BR14WR14DR1415R15BR15WR15DR156332 3116 158 700RFLAGS513-309.epsRIP6332 310* Not addressable whena REX prefix is used.** Only addressable whena REX prefix is used.Figure 2-3.General Registers in 64-Bit ModeFor most instructions running in 64-bit mode, access to the extended GPRs requires a REX instructionprefix (page 11).Instruction Overview25AMD64 Technology24594—Rev.
3.13—July 2007Figure 2-4 shows the segment registers which, like the instruction pointer, are used by all instructions.In legacy and compatibility modes, all segments are accessible. In 64-bit mode, which uses the flat(non-segmented) memory model, only the CS, FS, and GS segments are recognized, whereas thecontents of the DS, ES, and SS segment registers are ignored (the base for each of these segments isassumed to be zero, and neither their segment limit nor attributes are checked). For details, see“Segmented Virtual Memory” in Volume 2.Legacy Mode andCompatibility ModeCSCS1564-BitMode(Attributes only)DSignoredESignoredFS(Base only)GS(Base only)SSignoredFSGS0150513-312.epsFigure 2-4.Segment RegistersData Types.
Figure 2-5 on page 27 shows the general-purpose data types. They are all scalar, integerdata types. The 64-bit (quadword) data types are only available in 64-bit mode, and for mostinstructions they require a REX instruction prefix.26Instruction Overview24594—Rev. 3.13—July 2007AMD64 TechnologySigned Integer1270DoubleQuadword16 bytes (64-bit mode only)ss8 bytes (64-bit mode only)63s4 bytes31s2 bytes15sQuadwordDoublewordWordByte70Unsigned Integer1270DoubleQuadword16 bytes (64-bit mode only)8 bytes (64-bit mode only)63Quadword4 bytes31Doubleword2 bytesWord15BytePacked BCDBCD Digit73Bit513-326.eps0Figure 2-5.General-Purpose Data Types2.3.2 System InstructionsRegisters.
The system instructions use several specialized registers shown in Figure 2-6 on page 28.System software uses these registers to, among other things, manage the processor’s operatingenvironment, define system resource characteristics, and monitor software execution. With theexception of the RFLAGS register, system registers can be read and written only from privilegedsoftware.All system registers are 64 bits wide, except for the descriptor-table registers and the task register,which include 64-bit base-address fields and other fields.Instruction Overview27AMD64 Technology24594—Rev.
3.13—July 2007Control RegistersExtended-Feature-Enable RegisterMemory-Typing RegistersCR0EFERMTRRcapCR2MTRRdefTypeCR3System-Configuration RegisterMTRRphysBasenCR4SYSCFGMTRRphysMasknMTRRfixnCR8System-Flags RegisterRFLAGSSystem-Linkage RegistersPATSTARTOP_MEMLSTARTOP_MEM2CSTARSFMASKPerformance-Monitoring RegistersDebug RegistersFS.baseTSCDR0GS.basePerfEvtSelnDR1KernelGSbasePerfCtrnDR2SYSENTER_CSDR3SYSENTER_ESPMachine-Check RegistersDR6SYSENTER_EIPMCG_CAPMCG_STATDR7Debug-Extension RegistersDescriptor-Table RegistersGDTRIDTRLDTRDebugCtlMSRLastBranchFromIPLastBranchToIPLastIntFromIPMCG_CTLMCi_CTLMCi_STATUSMCi_ADDRMCi_MISCLastIntToIPModel-Specific RegistersTask RegisterTR513-260.epsFigure 2-6.
System RegistersData Structures. Figure 2-7 on page 29 shows the system data structures. These are created andmaintained by system software for use in protected mode. A processor running in protected mode usesthese data structures to manage memory and protection, and to store program-state information whenan interrupt or task switch occurs.28Instruction Overview24594—Rev. 3.13—July 2007AMD64 TechnologySegment Descriptors (Contained in Descriptor Tables)CodeGateStackTask-State SegmentDataLocal-Descriptor TableTask-State SegmentDescriptor TablesGlobal-Descriptor TableInterrupt-Descriptor TableLocal-Descriptor TableDescriptorGate DescriptorDescriptorDescriptorGate DescriptorDescriptor.........DescriptorGate DescriptorDescriptorPage-Translation TablesPage-Map Level-4Page-Directory PointerPage DirectoryPage Table513-261.epsFigure 2-7.System Data Structures2.3.3 128-Bit Media InstructionsRegisters.
The 128-bit media instructions use the 128-bit XMM registers. The number of availableXMM data registers depends on the operating mode, as shown in Figure 2-8 on page 30. In legacy andcompatibility modes, the eight legacy XMM data registers (XMM0–XMM7) are available. In 64-bitmode, eight additional XMM data registers (XMM8–XMM15) are available when a REX instructionprefix is used.The MXCSR register contains floating-point and other control and status flags used by the 128-bitmedia instructions. Some 128-bit media instructions also use the GPR (Figure 2-2 and Figure 2-3) andInstruction Overview29AMD64 Technology24594—Rev.
3.13—July 2007the MMX registers (Figure 2-10 on page 32) or set or clear flags in the rFLAGS register (seeFigure 2-2 and Figure 2-3).XMM Data Registers1270xmm0xmm1xmm2xmm3xmm4xmm5xmm6xmm7xmm8xmm9xmm10xmm11xmm12xmm13xmm14xmm15Available in all modesAvailable only in 64-bit mode128-Bit Media Control and Status RegisterMXCSR310513-314.epsFigure 2-8. 128-Bit Media RegistersData Types. Figure 2-9 on page 31 shows the 128-bit media data types. They include floating-pointand integer vectors and floating-point scalars. The floating-point data types include IEEE-754 singleprecision and double precision types.30Instruction Overview24594—Rev.
3.13—July 2007AMD64 TechnologyVector (Packed) Floating-Point Double Precision and Single Precision127115ssexpssexp63significandsignificand127ss118exp95significand8651ssexpssexp630significandsignificandss54exp31significand220Vector (Packed) Signed Integer Quadword, Doubleword, Word, Bytequadwordssdoublewordsswordssssbyte127bytess119bytess111doublewordsswordssbytesswordss103ssquadwordssbyte95ssbyte87sssswordbyte79doublewordssssbyte71sssswordbyte63ssbyte55sssswordbyte47doublewordsssswordssbyte39ssbyte31ssssbyte23sswordbyte15ssbyte70Vector (Packed) Unsigned Integer Quadword, Doubleword, Word, Bytequadwordquadworddoublewordwordbyte127byte119doublewordwordbyte111wordbyte103byte95wordbyte87doublewordbyte79wordbyte71byte63wordbyte55doublewordbyte47wordbyte39byte31wordbyte23byte15byte70Scalar Floating-Point Double Precision and Single Precisionssexp63significand51sssignificandexp31220Scalar Unsigned Integers127double quadword1270quadworddoubleword6331word15byte7bit0513-316.epsFigure 2-9.
128-Bit Media Data TypesInstruction Overview31AMD64 Technology24594—Rev. 3.13—July 20072.3.4 64-Bit Media InstructionsRegisters. The 64-bit media instructions use the eight 64-bit MMX registers, as shown inFigure 2-10. These registers are mapped onto the x87 floating-point registers, and 64-bit mediainstructions write the x87 tag word in a way that prevents an x87 instruction from using MMX data.Some 64-bit media instructions also use the GPR (Figure 2-2 and Figure 2-3) and the XMM registers(Figure 2-8).MMX Data Registers630mmx0mmx1mmx2mmx3mmx4mmx5mmx6mmx7513-327.epsFigure 2-10.
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