Volume 3 General-Purpose and System Instructions (794097), страница 16
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Otherwise, itdoes not change the AH register and clears the CF and AF flags to 0. In either case, AAA clears bits7–4 of the AL register, leaving the correct decimal digit in bits 3–0.This instruction also makes it possible to add ASCII numbers without having to mask off the uppernibble ‘3’.MXCSR Flags AffectedUsing this instruction in 64-bit mode generates an invalid-opcode exception.MnemonicOpcodeAAADescriptionCreate an unpacked BCD number.(Invalid in 64-bit mode.)37Related InstructionsAAD, AAM, AASrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFUUMUM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode, #UDInstruction ReferenceXCause of ExceptionThis instruction was executed in 64-bit mode.AAA53AMD64 Technology24594—Rev.
3.13—July 2007AADASCII Adjust Before DivisionConverts two unpacked BCD digits in the AL (least significant) and AH (most significant) registers toa single binary value in the AL register using the following formula:AL = ((10d * AH) + (AL))After the conversion, AH is cleared to 00h.In most modern assemblers, the AAD instruction adjusts from base-10 values. However, by coding theinstruction directly in binary, it can adjust from any base specified by the immediate byte value (ib)suffixed onto the D5h opcode. For example, code D508h for octal, D50Ah for decimal, and D50Ch forduodecimal (base 12).Using this instruction in 64-bit mode generates an invalid-opcode exception.MnemonicOpcodeDescriptionAADD5 0AAdjust two BCD digits in AL and AH.(Invalid in 64-bit mode.)(None)D5 ibAdjust two BCD digits to the immediate byte base.(Invalid in 64-bit mode.)Related InstructionsAAA, AAM, AASrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFMMUMU76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionInvalid opcode, #UD54VirtualReal 8086 ProtectedXCause of ExceptionThis instruction was executed in 64-bit mode.AADInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyAAMASCII Adjust After MultiplyConverts the value in the AL register from binary to two unpacked BCD digits in the AH (mostsignificant) and AL (least significant) registers using the following formula:AH = (AL/10d)AL = (AL mod 10d)In most modern assemblers, the AAM instruction adjusts to base-10 values.
However, by coding theinstruction directly in binary, it can adjust to any base specified by the immediate byte value (ib)suffixed onto the D4h opcode. For example, code D408h for octal, D40Ah for decimal, and D40Ch forduodecimal (base 12).Using this instruction in 64-bit mode generates an invalid-opcode exception.MnemonicOpcodeDescriptionAAMD4 0ACreate a pair of unpacked BCD values in AH and AL.(Invalid in 64-bit mode.)(None)D4 ibCreate a pair of unpacked values to the immediate bytebase.(Invalid in 64-bit mode.)Related InstructionsAAA, AAD, AASrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFMMUMU76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M. Unaffected flags are blank. Undefinedflags are U.ExceptionsExceptionDivide by zero, #DEVirtualReal 8086 ProtectedXInvalid opcode, #UDInstruction ReferenceXCause of ExceptionX8-bit immediate value was 0.XThis instruction was executed in 64-bit mode.AAM55AMD64 Technology24594—Rev. 3.13—July 2007AASASCII Adjust After SubtractionAdjusts the value in the AL register to an unpacked BCD value.
Use the AAS instruction after usingthe SUB instruction to subtract two unpacked BCD numbers.If the value in AL is greater than 9 or the AF flag is set to 1, the instruction decrements the value in AH,subtracts 6 from the AL register, and sets the CF and AF flags to 1. Otherwise, it clears the CF and AFflags and the AH register is unchanged. In either case, the instruction clears bits 7–4 of the AL register,leaving the correct decimal digit in bits 3–0.Using this instruction in 64-bit mode generates an invalid-opcode exception.MnemonicOpcodeAASDescriptionCreate an unpacked BCD number from the contents ofthe AL register.(Invalid in 64-bit mode.)3FRelated InstructionsAAA, AAD, AAMrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFUUMUM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionInvalid opcode, #UD56VirtualReal 8086 ProtectedXCause of ExceptionThis instruction was executed in 64-bit mode.AASInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyADCAdd with CarryAdds the carry flag (CF), the value in a register or memory location (first operand), and an immediatevalue or the value in a register or memory location (second operand), and stores the result in the firstoperand location.
The instruction cannot add two memory operands. The CF flag indicates a pendingcarry from a previous addition operation. The instruction sign-extends an immediate value to thelength of the destination register or memory location.This instruction evaluates the result for both signed and unsigned data types and sets the OF and CFflags to indicate a carry in a signed or unsigned result, respectively. It sets the SF flag to indicate thesign of a signed result.Use the ADC instruction after an ADD instruction as part of a multibyte or multiword addition.The forms of the ADC instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionADC AL, imm814 ibAdd imm8 to AL + CF.ADC AX, imm1615 iwAdd imm16 to AX + CF.ADC EAX, imm3215 idAdd imm32 to EAX + CF.ADC RAX, imm3215 idAdd sign-extended imm32 to RAX + CF.ADC reg/mem8, imm880 /2 ibAdd imm8 to reg/mem8 + CF.ADC reg/mem16, imm1681 /2 iwAdd imm16 to reg/mem16 + CF.ADC reg/mem32, imm3281 /2 idAdd imm32 to reg/mem32 + CF.ADC reg/mem64, imm3281 /2 idAdd sign-extended imm32 to reg/mem64 + CF.ADC reg/mem16, imm883 /2 ibAdd sign-extended imm8 to reg/mem16 + CF.ADC reg/mem32, imm883 /2 ibAdd sign-extended imm8 to reg/mem32 + CF.ADC reg/mem64, imm883 /2 ibAdd sign-extended imm8 to reg/mem64 + CF.ADC reg/mem8, reg810 /rAdd reg8 to reg/mem8 + CFADC reg/mem16, reg1611 /rAdd reg16 to reg/mem16 + CF.ADC reg/mem32, reg3211 /rAdd reg32 to reg/mem32 + CF.ADC reg/mem64, reg6411 /rAdd reg64 to reg/mem64 + CF.ADC reg8, reg/mem812 /rAdd reg/mem8 to reg8 + CF.ADC reg16, reg/mem1613 /rAdd reg/mem16 to reg16 + CF.ADC reg32, reg/mem3213 /rAdd reg/mem32 to reg32 + CF.ADC reg64, reg/mem6413 /rAdd reg/mem64 to reg64 + CF.Instruction ReferenceADC57AMD64 Technology24594—Rev.
3.13—July 2007Related InstructionsADD, SBB, SUBrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.58ADCInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyADDSigned or Unsigned AddAdds the value in a register or memory location (first operand) and an immediate value or the value ina register or memory location (second operand), and stores the result in the first operand location. Theinstruction cannot add two memory operands. The instruction sign-extends an immediate value to thelength of the destination register or memory operand.This instruction evaluates the result for both signed and unsigned data types and sets the OF and CFflags to indicate a carry in a signed or unsigned result, respectively.
It sets the SF flag to indicate thesign of a signed result.The forms of the ADD instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionADD AL, imm804 ibAdd imm8 to AL.ADD AX, imm1605 iwAdd imm16 to AX.ADD EAX, imm3205 idAdd imm32 to EAX.ADD RAX, imm3205 idAdd sign-extended imm32 to RAX.ADD reg/mem8, imm880 /0 ibAdd imm8 to reg/mem8.ADD reg/mem16, imm1681 /0 iwAdd imm16 to reg/mem16ADD reg/mem32, imm3281 /0 idAdd imm32 to reg/mem32.ADD reg/mem64, imm3281 /0 idAdd sign-extended imm32 to reg/mem64.ADD reg/mem16, imm883 /0 ibAdd sign-extended imm8 to reg/mem16ADD reg/mem32, imm883 /0 ibAdd sign-extended imm8 to reg/mem32.ADD reg/mem64, imm883 /0 ibAdd sign-extended imm8 to reg/mem64.ADD reg/mem8, reg800 /rAdd reg8 to reg/mem8.ADD reg/mem16, reg1601 /rAdd reg16 to reg/mem16.ADD reg/mem32, reg3201 /rAdd reg32 to reg/mem32.ADD reg/mem64, reg6401 /rAdd reg64 to reg/mem64.ADD reg8, reg/mem802 /rAdd reg/mem8 to reg8.ADD reg16, reg/mem1603 /rAdd reg/mem16 to reg16.ADD reg32, reg/mem3203 /rAdd reg/mem32 to reg32.ADD reg64, reg/mem6403 /rAdd reg/mem64 to reg64.Related InstructionsADC, SBB, SUBInstruction ReferenceADD59AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.60ADDInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyANDLogical ANDPerforms a bitwise AND operation on the value in a register or memory location (first operand) and animmediate value or the value in a register or memory location (second operand), and stores the result inthe first operand location.
The instruction cannot AND two memory operands.The instruction sets each bit of the result to 1 if the corresponding bit of both operands is set;otherwise, it clears the bit to 0. The following table shows the truth table for the AND operation:XYX AND Y000010100111The forms of the AND instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionAND AL, imm824 ibAND the contents of AL with an immediate 8-bit valueand store the result in AL.AND AX, imm1625 iwAND the contents of AX with an immediate 16-bit valueand store the result in AX.AND EAX, imm3225 idAND the contents of EAX with an immediate 32-bitvalue and store the result in EAX.AND RAX, imm3225 idAND the contents of RAX with a sign-extendedimmediate 32-bit value and store the result in RAX.AND reg/mem8, imm880 /4 ibAND the contents of reg/mem8 with imm8.AND reg/mem16, imm1681 /4 iwAND the contents of reg/mem16 with imm16.AND reg/mem32, imm3281 /4 idAND the contents of reg/mem32 with imm32.AND reg/mem64, imm3281 /4 idAND the contents of reg/mem64 with sign-extendedimm32.AND reg/mem16, imm883 /4 ibAND the contents of reg/mem16 with a sign-extended8-bit value.AND reg/mem32, imm883 /4 ibAND the contents of reg/mem32 with a sign-extended8-bit value.AND reg/mem64, imm883 /4 ibAND the contents of reg/mem64 with a sign-extended8-bit value.AND reg/mem8, reg820 /rAND the contents of an 8-bit register or memorylocation with the contents of an 8-bit register.Instruction ReferenceAND61AMD64 Technology24594—Rev.
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