Volume 3 General-Purpose and System Instructions (794097), страница 13
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64-Bit Media RegistersData Types. Figure 2-11 on page 33 shows the 64-bit media data types. They include floating-pointand integer vectors and integer scalars. The floating-point data type, used by 3DNow! instructions,consists of a packed vector or two IEEE-754 32-bit single-precision data types.
Unlike other kinds offloating-point instructions, however, the 3DNow!™ instructions do not generate floating-pointexceptions. For this reason, there is no register for reporting or controlling the status of exceptions inthe 64-bit-media instruction subset.32Instruction Overview24594—Rev. 3.13—July 2007AMD64 TechnologyVector (Packed) Single-Precision Floating-Pointexpss63significandss54expsignificand31220Vector (Packed) Signed Integersdoublewordsswordssbytess63ssssbyte55sswordbyte47doublewordssssbyte39wordssssbyte31ssbyte23wordssssbyte15ssbyte70Vector (Packed) Unsigned Integersdoublewordwordbyte63wordbyte55doublewordbyte47wordbyte39byte31wordbyte23byte15byte70Signed Integerssquadword63sdoubleword31sword15sbyte70Unsigned Integersquadword63doubleword31word15byte7513-319.eps0Figure 2-11.
64-Bit Media Data TypesInstruction Overview33AMD64 Technology24594—Rev. 3.13—July 20072.3.5 x87 Floating-Point InstructionsRegisters. The x87 floating-point instructions use the x87 registers shown in Figure 2-12. There areeight 80-bit data registers, three 16-bit registers that hold the x87 control word, status word, and tagword, and three registers (last instruction pointer, last opcode, last data pointer) that hold informationabout the last x87 operation.The physical data registers are named FPR0–FPR7, although x87 software references these registers asa stack of registers, named ST(0)–ST(7). The x87 instructions store operands only in their own 80-bitfloating-point registers or in memory.
They do not access the GPR or XMM registers.x87 Data Registers790fpr0fpr1fpr2fpr3fpr4fpr5fpr6fpr763Instruction Pointer (rIP)ControlControlWordWordData Pointer (rDP)StatusStatusWordWordOpcode10TagTagWordWord0150513-321.epsFigure 2-12. x87 RegistersData Types. Figure 2-13 on page 35 shows all x87 data types. They include three floating-pointformats (80-bit double-extended precision, 64-bit double precision, and 32-bit single precision), threesigned-integer formats (quadword, doubleword, and word), and an 80-bit packed binary-codeddecimal (BCD) format.34Instruction Overview24594—Rev.
3.13—July 2007AMD64 TechnologyFloating-Point79s063exp79s63Double-ExtendedPrecisionsignificandiexpDouble Precisionsignificand51sexp31Single Precisionsignificand220Signed Integer8 bytess63Quadwords4 bytes31s15Doubleword2 bytesWord0Binary-Coded Decimal (BCD)Packed Decimalss79710513-317.epsFigure 2-13. x87 Data Types2.4Summary of ExceptionsTable 2-1 on page 36 lists all possible exceptions. The table shows the interrupt-vector numbers,names, mnemonics, source, and possible causes. Exceptions that apply to specific instructions aredocumented with each instruction in the instruction-detail pages that follow.Instruction Overview35AMD64 TechnologyTable 2-1.Vector24594—Rev. 3.13—July 2007Interrupt-Vector Source and CauseInterrupt (Exception)MnemonicSource0Divide-By-Zero-Error#DESoftware DIV, IDIV, AAM instructions1Debug#DBInternalInstruction accesses and data accesses2Non-Maskable-Interrupt#NMIExternalExternal NMI signal3Breakpoint#BPSoftware INT3 instruction4Overflow#OFSoftware INTO instruction5Bound-Range#BRSoftware BOUND instruction6Invalid-Opcode#UDInternalInvalid instructions7Device-Not-Available#NMInternalx87 instructions8Double-Fault#DFInternalInterrupt during an interrupt9Coprocessor-Segment-Overrun—ExternalUnsupported (reserved)10Invalid-TSS#TSInternalTask-state segment access and taskswitch11Segment-Not-Present#NPInternalSegment access through a descriptor12Stack#SSInternalSS register loads and stack references13General-Protection#GPInternalMemory accesses and protectionchecks14Page-Fault#PFInternalMemory accesses when pagingenabled15Reserved16Floating-Point ExceptionPending#MFSoftwarex87 floating-point and 64-bit mediafloating-point instructions17Alignment-Check#ACInternalMemory accesses18Machine-Check#MCInternalExternalModel specific19SIMD Floating-Point#XFInternal128-bit media floating-point instructions—20—29 Reserved (Internal and External)30SVM Security Exception31Reserved (Internal and External)0—255 External Interrupts (Maskable)0—255 Software Interrupts36Cause—#SXExternalSecurity-Sensitive Events—#INTR—ExternalExternal interrupt signalSoftware INTn instructionInstruction Overview24594—Rev.
3.13—July 20072.5AMD64 TechnologyNotation2.5.1 Mnemonic SyntaxEach instruction has a syntax that includes the mnemonic and any operands that the instruction cantake. Figure 2-14 on page 37 shows an example of a syntax in which the instruction takes twooperands. In most instructions that take two operands, the first (left-most) operand is both a sourceoperand (the first source operand) and the destination operand.
The second (right-most) operandserves only as a source, not a destination.ADDPD xmm1, xmm2/mem128MnemonicFirst Source Operandand Destination OperandSecond Source OperandFigure 2-14.513-322.epsSyntax for Typical Two-Operand InstructionThe following notation is used to denote the size and type of source and destination operands:•••••••••••••••cReg—Control register.dReg—Debug register.imm8—Byte (8-bit) immediate.imm16—Word (16-bit) immediate.imm16/32—Word (16-bit) or doubleword (32-bit) immediate.imm32—Doubleword (32-bit) immediate.imm32/64—Doubleword (32-bit) or quadword (64-bit) immediate.imm64—Quadword (64-bit) immediate.mem—An operand of unspecified size in memory.mem8—Byte (8-bit) operand in memory.mem16—Word (16-bit) operand in memory.mem16/32—Word (16-bit) or doubleword (32-bit) operand in memory.mem32—Doubleword (32-bit) operand in memory.mem32/48—Doubleword (32-bit) or 48-bit operand in memory.mem48—48-bit operand in memory.Instruction Overview37AMD64 Technology24594—Rev.
3.13—July 2007•••••mem64—Quadword (64-bit) operand in memory.mem128—Double quadword (128-bit) operand in memory.mem16:16—Two sequential word (16-bit) operands in memory.mem16:32—A doubleword (32-bit) operand followed by a word (16-bit) operand in memory.mem32real—Single-precision (32-bit) floating-point operand in memory.mem32int—Doubleword (32-bit) integer operand in memory.mem64real—Double-precision (64-bit) floating-point operand in memory.mem64int—Quadword (64-bit) integer operand in memory.mem80real—Double-extended-precision (80-bit) floating-point operand in memory.mem80dec—80-bit packed BCD operand in memory, containing 18 4-bit BCD digits.mem2env—16-bit x87 control word or x87 status word.mem14/28env—14-byte or 28-byte x87 environment.
The x87 environment consists of the x87control word, x87 status word, x87 tag word, last non-control instruction pointer, last data pointer,and opcode of the last non-control instruction completed.mem94/108env—94-byte or 108-byte x87 environment and register stack.mem512env—512-byte environment for 128-bit media, 64-bit media, and x87 instructions.mmx—Quadword (64-bit) operand in an MMX register.mmx1—Quadword (64-bit) operand in an MMX register, specified as the left-most (first) operandin the instruction syntax.mmx2—Quadword (64-bit) operand in an MMX register, specified as the right-most (second)operand in the instruction syntax.mmx/mem32—Doubleword (32-bit) operand in an MMX register or memory.mmx/mem64—Quadword (64-bit) operand in an MMX register or memory.mmx1/mem64—Quadword (64-bit) operand in an MMX register or memory, specified as the leftmost (first) operand in the instruction syntax.mmx2/mem64—Quadword (64-bit) operand in an MMX register or memory, specified as the rightmost (second) operand in the instruction syntax.moffset—Direct memory offset that specifies an operand in memory.moffset8—Direct memory offset that specifies a byte (8-bit) operand in memory.moffset16—Direct memory offset that specifies a word (16-bit) operand in memory.moffset32—Direct memory offset that specifies a doubleword (32-bit) operand in memory.moffset64—Direct memory offset that specifies a quadword (64-bit) operand in memory.••••pntr16:16—Far pointer with 16-bit selector and 16-bit offset.pntr16:32—Far pointer with 16-bit selector and 32-bit offset.reg—Operand of unspecified size in a GPR register.reg8—Byte (8-bit) operand in a GPR register.•••••••••••••••••••••38Instruction Overview24594—Rev.
3.13—July 2007•••••••••••••••••••••AMD64 Technologyreg16—Word (16-bit) operand in a GPR register.reg16/32—Word (16-bit) or doubleword (32-bit) operand in a GPR register.reg32—Doubleword (32-bit) operand in a GPR register.reg64—Quadword (64-bit) operand in a GPR register.reg/mem8—Byte (8-bit) operand in a GPR register or memory.reg/mem16—Word (16-bit) operand in a GPR register or memory.reg/mem32—Doubleword (32-bit) operand in a GPR register or memory.reg/mem64—Quadword (64-bit) operand in a GPR register or memory.rel8off—Signed 8-bit offset relative to the instruction pointer.rel16off—Signed 16-bit offset relative to the instruction pointer.rel32off—Signed 32-bit offset relative to the instruction pointer.segReg or sReg—Word (16-bit) operand in a segment register.ST(0)—x87 stack register 0.ST(i)—x87 stack register i, where i is between 0 and 7.xmm—Double quadword (128-bit) operand in an XMM register.xmm1—Double quadword (128-bit) operand in an XMM register, specified as the left-most (first)operand in the instruction syntax.xmm2—Double quadword (128-bit) operand in an XMM register, specified as the right-most(second) operand in the instruction syntax.xmm/mem64—Quadword (64-bit) operand in a 128-bit XMM register or memory.xmm/mem128—Double quadword (128-bit) operand in an XMM register or memory.xmm1/mem128—Double quadword (128-bit) operand in an XMM register or memory, specified asthe left-most (first) operand in the instruction syntax.xmm2/mem128—Double quadword (128-bit) operand in an XMM register or memory, specified asthe right-most (second) operand in the instruction syntax.2.5.2 Opcode SyntaxIn addition to the notation shown above in “Mnemonic Syntax” on page 37, the following notationindicates the size and type of operands in the syntax of an instruction opcode:•••/digit—Indicates that the ModRM byte specifies only one register or memory (r/m) operand.
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