Volume 3 General-Purpose and System Instructions (794097), страница 15
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3.13—July 2007AMD64 TechnologyIF ((PAGING_ENABLED) && (temp_linear is on a not-present page))EXCEPTION [#PF(error_code)]// page fault for not-present pagememory [temp_linear].x = temp.x// write the bytes to memory/////////////////////////////////////////////////////////////////////////////////// PUSH // Write data to the stack/////////////////////////////////////////////////////////////////////////////////usage:PUSH.x temp// where x is one of these: {v, z, b, w, d, q} and// denotes the size of the pushdefinition:WRITE_MEM.x [SS:RSP.s - X] = temp.xRSP.s = RSP - X// write to the stack// point rsp to the data just written/////////////////////////////////////////////////////////////////////////////////// POP // Read data from the stack, zero-extend it to 64 bits/////////////////////////////////////////////////////////////////////////////////usage:POP.x temp// where x is one of these: {v, z, b, w, d, q} and// denotes the size of the popdefinition:temp = READ_MEM.x [SS:RSP.s]RSP.s = RSP + X// read from the stack// point rsp above the data just written/////////////////////////////////////////////////////////////////////////////////// READ_DESCRIPTOR // Read 8-byte descriptor from GDT/LDT, return the descriptor/////////////////////////////////////////////////////////////////////////////////usage:temp_descriptor = READ_DESCRIPTOR (selector, chktype)// chktype field is one of the following:// cs_chkused for far call and far jump// clg_chkused when reading CS for far call or far jump through call gate// ss_chkused when reading SS// iret_chkused when reading CS for IRET or RETF// intcs_chk used when readin the CS for interrupts and exceptionsdefinition:temp_offset = selector AND 0xfff8Instruction Overview// upper 13 bits give an offset47AMD64 Technology24594—Rev.
3.13—July 2007// in the descriptor tableIF (selector.TI = 0)// read 8 bytes from the gdt, split it into// (base,limit,attr) if the type bitstemp_desc = READ_MEM.q [gdt:temp_offset]// indicate a block of memory, or split// it into (segment,offset,attr)// if the type bits indicate// a gate, and save the result in temp_descELSEtemp_desc = READ_MEM.q [ldt:temp_offset]// read 8 bytes from the ldt, split it into// (base,limit,attr) if the type bits// indicate a block of memory, or split// it into (segment,offset,attr) if the type// bits indicate a gate, and save the result// in temp_descIF (selector.rpl or temp_desc.attr.dpl is illegal for the current mode/cpl)EXCEPTION [#GP(selector)]IF (temp_desc.attr.type is illegal for the current mode/chktype)EXCEPTION [#GP(selector)]IF (temp_desc.attr.p=0)EXCEPTION [#NP(selector)]RETURN (temp_desc)/////////////////////////////////////////////////////////////////////////////////// READ_IDT // Read an 8-byte descriptor from the IDT, return the descriptor/////////////////////////////////////////////////////////////////////////////////usage:temp_idt_desc = READ_IDT (vector)// "vector" is the interrupt vector numberdefinition:IF (LONG_MODE)// long-mode idt descriptors are 16 bytes longtemp_offset = vector*16ELSE // (LEGACY_MODE) legacy-protected-mode idt descriptors are 8 bytes longtemp_offset = vector*8temp_desc = READ_MEM.q [idt:temp_offset]// read 8 bytes from the idt, split it into// (segment,offset,attr), and save it in temp_descIF (temp_desc.attr.dpl is illegal for the current mode/cpl)// exception, with error code that indicates this idt gate48Instruction Overview24594—Rev.
3.13—July 2007AMD64 TechnologyEXCEPTION [#GP(vector*8+2)]IF (temp_desc.attr.type is illegal for the current mode)// exception, with error code that indicates this idt gateEXCEPTION [#GP(vector*8+2)]IF (temp_desc.attr.p=0)EXCEPTION [#NP(vector*8+2)]// segment-not-present exception, with an error code that// indicates this idt gateRETURN (temp_desc)/////////////////////////////////////////////////////////////////////////////////// READ_INNER_LEVEL_STACK_POINTER// Read a new stack pointer (rsp or ss:esp) from the tss/////////////////////////////////////////////////////////////////////////////////usage:temp_SS_desc:temp_RSP = READ_INNER_LEVEL_STACK_POINTER (new_cpl, ist_index)definition:IF (LONG_MODE){IF (ist_index>0)// if IST is selected, read an ISTn stack pointer from the tsstemp_RSP = READ_MEM.q [tss:ist_index*8+28]ELSE // (ist_index=0)// otherwise read an RSPn stack pointer from the tsstemp_RSP = READ_MEM.q [tss:new_cpl*8+4]temp_SS_desc.sel = NULL + new_cpl// in long mode, changing to lower cpl sets SS.sel to// NULL+new_cpl}ELSE // (LEGACY_MODE){temp_RSP = READ_MEM.d [tss:new_cpl*8+4]// read ESPn from the tsstemp_sel = READ_MEM.d [tss:new_cpl*8+8]// read SSn from the tsstemp_SS_desc = READ_DESCRIPTOR (temp_sel, ss_chk)}return (temp_RSP:temp_SS_desc)Instruction Overview49AMD64 Technology24594—Rev.
3.13—July 2007/////////////////////////////////////////////////////////////////////////////////// READ_BIT_ARRAY // Read 1 bit from a bit array in memory/////////////////////////////////////////////////////////////////////////////////usage:temp_value = READ_BIT_ARRAY ([mem], bit_number)definition:temp_BYTE = READ_MEM.b [mem + (bit_number SHR 3)]// read the byte containing the bittemp_BIT = temp_BYTE SHR (bit_number & 7)// shift the requested bit position into bit 0return (temp_BIT & 0x01)50// return ’0’ or ’1’Instruction Overview24594—Rev.
3.13—July 20073AMD64 TechnologyGeneral-Purpose Instruction ReferenceThis chapter describes the function, mnemonic syntax, opcodes, affected flags, and possibleexceptions generated by the general-purpose instructions. General-purpose instructions are used inbasic software execution. Most of these instructions load, store, or operate on data located in thegeneral-purpose registers (GPRs), in memory, or in both. The remaining instructions are used to alterthe sequential flow of the program by branching to other locations within the program, or to entirelydifferent programs.
With the exception of the MOVD, MOVMSKPD and MOVMSKPS instructions,which operate on MMX/XMM registers, the instructions within the category of general-purposeinstructions do not operate on any other register set.Most general-purpose instructions are supported in all hardware implementations of the AMD64architecture, however it may be necessary to use the CPUID instruction to test for support for a smallset of general-purpose instructions. These instructions are listed in Table 3-1, along with the CPUIDfunction, the register and bit used to test for the presence of the instruction.Table 3-1.Instruction Support Indicated by CPUID Feature BitsInstructionRegister[Bit]Feature MnemonicCPUID Function(s)CMPXCHG8BEDX[8]CMPXCHG8B0000_0001h, 8000_0001hCMPXCHG16BECX[13]CMPXCHG16B0000_0001hCMOVcc (Conditional Moves)EDX[15]CMOV0000_0001h, 8000_0001hCLFLUSHEDX[19]CLFSH0000_0001hLZCNTECX[5]Advanced BitManipulation (ABM)8000_0001hLong Mode instructionsEDX[29]Long Mode (LM)8000_0001hMFENCE, LFENCEEDX[26]SSE20000_0001hEDX[25]SSEEDX[26]SSE2MOVNTIEDX[26]SSE20000_0001hPOPCNTECX[23]POPCNT0000_0001hECX[8]3DNow!™ PrefetchEDX[29]LMEDX[31]3DNow!™EDX[25]FXSRMOVDPREFETCH/WSFENCE0000_0001h8000_0001h0000_0001hThe general-purpose instructions can be used in legacy mode or 64-bit long mode.
Compilation ofgeneral-purpose programs for execution in 64-bit long mode offers three primary advantages: access tothe eight extended, 64-bit general-purpose registers (for a register set consisting of GPR0–GPR15),access to the 64-bit virtual address space, and access to the RIP-relative addressing mode.For further information about the general-purpose instructions and register resources, see:Instruction Reference51AMD64 Technology•••••5224594—Rev. 3.13—July 2007“General-Purpose Programming” in Volume 1.“Summary of Registers and Data Types” on page 24.“Notation” on page 37.“Instruction Prefixes” on page 3.Appendix B, “General-Purpose Instructions in 64-Bit Mode.” In particular, see “General Rules for64-Bit Mode” on page 373.Instruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyAAAASCII Adjust After AdditionAdjusts the value in the AL register to an unpacked BCD value. Use the AAA instruction after usingthe ADD instruction to add two unpacked BCD numbers.If the value in the lower nibble of AL is greater than 9 or the AF flag is set to 1, the instructionincrements the AH register, adds 6 to the AL register, and sets the CF and AF flags to 1.
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