Volume 3 General-Purpose and System Instructions (794097), страница 21
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Such reordering can invalidate aspeculatively prefetched cache line, unintentionally defeating the prefetch operation. The only way toavoid this situation is to use the MFENCE instruction after the CLFLUSH instruction to force strongordering of the CLFLUSH instruction with respect to subsequent memory operations.
The CLFLUSHinstruction may also take effect on a cache line while stores from previous store instructions are stillpending in the store buffer. To ensure that such stores are included in the cache line that is flushed, usean MFENCE instruction ahead of the CLFLUSH instruction. Such stores would otherwise cause theline to be re-cached and modified after the CLFLUSH completed. The LFENCE, SFENCE, andserializing instructions are not ordered with respect to CLFLUSH.The CLFLUSH instruction behaves like a load instruction with respect to setting the page-tableaccessed and dirty bits. That is, it sets the page-table accessed bit to 1, but does not set the page-tabledirty bit.The CLFLUSH instruction is supported if CPUID function 0000_0001h sets EDX bit 19. CPUIDfunction 0000_0001h returns the CLFLUSH size in EBX bits 23:16.
This value reports the size of aline flushed by CLFLUSH in quadwords. See CPUID for details.The CLFLUSH instruction executes at any privilege level. CLFLUSH performs all the segmentationand paging checks that a 1-byte read would perform, except that it also allows references to executeonly segments.MnemonicCFLUSH mem8Opcode0F AE /7Descriptionflush cache line containing mem8.Related InstructionsINVD, WBINVD88CLFLUSHInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyrFLAGS AffectedNoneExceptionsException (vector)RealVirtual8086 ProtectedCause of ExceptionInvalid opcode, #UDXXXThe CLFLUSH instruction is not supported, asindicated by EDX bit 19 of CPUID function0000_0001h.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XA page fault resulted from the execution of theinstruction.Page fault, #PFInstruction ReferenceXCLFLUSH89AMD64 Technology24594—Rev.
3.13—July 2007CMCComplement Carry FlagComplements (toggles) the carry flag (CF) bit of the rFLAGS register.MnemonicOpcodeCMCDescriptionF5Complement the carry flag (CF).Related InstructionsCLC, STCrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCFM2120191817161413–1211109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsNone90CMCInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyCMOVccConditional MoveConditionally moves a 16-bit, 32-bit, or 64-bit value in memory or a general-purpose register (secondoperand) into a register (first operand), depending upon the settings of condition flags in the rFLAGSregister.
If the condition is not satisfied, the instruction has no effect.The mnemonics of CMOVcc instructions denote the condition that must be satisfied. Most assemblersprovide instruction mnemonics with A (above) and B (below) tags to supply the semantics formanipulating unsigned integers. Those with G (greater than) and L (less than) tags deal with signedintegers. Many opcodes may be represented by synonymous mnemonics. For example, the CMOVLinstruction is synonymous with the CMOVNGE instruction and denote the instruction with the opcode0F 4C.Support for CMOVcc instructions depends on the processor implementation. To determine whether aprocessor can perform CMOVcc instructions, use the CPUID instruction to determine whether EDXbit 15 of CPUID function 0000_0001h or function 8000_0001h is set to 1.MnemonicOpcodeDescriptionCMOVO reg16, reg/mem16CMOVO reg32, reg/mem32CMOVO reg64, reg/mem640F 40 /rMove if overflow (OF = 1).CMOVNO reg16, reg/mem16CMOVNO reg32, reg/mem32CMOVNO reg64, reg/mem640F 41 /rMove if not overflow (OF = 0).CMOVB reg16, reg/mem16CMOVB reg32, reg/mem32CMOVB reg64, reg/mem640F 42 /rMove if below (CF = 1).CMOVC reg16, reg/mem16CMOVC reg32, reg/mem32CMOVC reg64, reg/mem640F 42 /rMove if carry (CF = 1).CMOVNAE reg16, reg/mem16CMOVNAE reg32, reg/mem32CMOVNAE reg64, reg/mem640F 42 /rMove if not above or equal (CF = 1).CMOVNB reg16,reg/mem16CMOVNB reg32,reg/mem32CMOVNB reg64,reg/mem640F 43 /rMove if not below (CF = 0).CMOVNC reg16,reg/mem16CMOVNC reg32,reg/mem32CMOVNC reg64,reg/mem640F 43 /rMove if not carry (CF = 0).CMOVAE reg16, reg/mem16CMOVAE reg32, reg/mem32CMOVAE reg64, reg/mem640F 43 /rMove if above or equal (CF = 0).CMOVZ reg16, reg/mem16CMOVZ reg32, reg/mem32CMOVZ reg64, reg/mem640F 44 /rMove if zero (ZF = 1).Instruction ReferenceCMOVcc91AMD64 TechnologyMnemonic24594—Rev.
3.13—July 2007OpcodeDescriptionCMOVE reg16, reg/mem16CMOVE reg32, reg/mem32CMOVE reg64, reg/mem640F 44 /rMove if equal (ZF =1).CMOVNZ reg16, reg/mem16CMOVNZ reg32, reg/mem32CMOVNZ reg64, reg/mem640F 45 /rMove if not zero (ZF = 0).CMOVNE reg16, reg/mem16CMOVNE reg32, reg/mem32CMOVNE reg64, reg/mem640F 45 /rMove if not equal (ZF = 0).CMOVBE reg16, reg/mem16CMOVBE reg32, reg/mem32CMOVBE reg64, reg/mem640F 46 /rMove if below or equal (CF = 1 or ZF = 1).CMOVNA reg16, reg/mem16CMOVNA reg32, reg/mem32CMOVNA reg64, reg/mem640F 46 /rMove if not above (CF = 1 or ZF = 1).CMOVNBE reg16, reg/mem16CMOVNBE reg32,reg/mem32CMOVNBE reg64,reg/mem640F 47 /rMove if not below or equal (CF = 0 and ZF = 0).CMOVA reg16, reg/mem16CMOVA reg32, reg/mem32CMOVA reg64, reg/mem640F 47 /rMove if above (CF = 0 and ZF = 0).CMOVS reg16, reg/mem16CMOVS reg32, reg/mem32CMOVS reg64, reg/mem640F 48 /rMove if sign (SF =1).CMOVNS reg16, reg/mem16CMOVNS reg32, reg/mem32CMOVNS reg64, reg/mem640F 49 /rMove if not sign (SF = 0).CMOVP reg16, reg/mem16CMOVP reg32, reg/mem32CMOVP reg64, reg/mem640F 4A /rMove if parity (PF = 1).CMOVPE reg16, reg/mem16CMOVPE reg32, reg/mem32CMOVPE reg64, reg/mem640F 4A /rMove if parity even (PF = 1).CMOVNP reg16, reg/mem16CMOVNP reg32, reg/mem32CMOVNP reg64, reg/mem640F 4B /rMove if not parity (PF = 0).CMOVPO reg16, reg/mem16CMOVPO reg32, reg/mem32CMOVPO reg64, reg/mem640F 4B /rMove if parity odd (PF = 0).CMOVL reg16, reg/mem16CMOVL reg32, reg/mem32CMOVL reg64, reg/mem640F 4C /rMove if less (SF <> OF).CMOVNGE reg16, reg/mem16CMOVNGE reg32, reg/mem32CMOVNGE reg64, reg/mem640F 4C /rMove if not greater or equal (SF <> OF).92CMOVccInstruction Reference24594—Rev.
3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionCMOVNL reg16, reg/mem16CMOVNL reg32, reg/mem32CMOVNL reg64, reg/mem640F 4D /rMove if not less (SF = OF).CMOVGE reg16, reg/mem16CMOVGE reg32, reg/mem32CMOVGE reg64, reg/mem640F 4D /rMove if greater or equal (SF = OF).CMOVLE reg16, reg/mem16CMOVLE reg32, reg/mem32CMOVLE reg64, reg/mem640F 4E /rMove if less or equal (ZF = 1 or SF <> OF).CMOVNG reg16, reg/mem16CMOVNG reg32, reg/mem32CMOVNG reg64, reg/mem640F 4E /rMove if not greater (ZF = 1 or SF <> OF).CMOVNLE reg16, reg/mem16CMOVNLE reg32, reg/mem32CMOVNLE reg64, reg/mem640F 4F /rMove if not less or equal (ZF = 0 and SF = OF).CMOVG reg16, reg/mem16CMOVG reg32, reg/mem32CMOVG reg64, reg/mem640F 4F /rMove if greater (ZF = 0 and SF = OF).Related InstructionsMOVrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionInvalid opcode, #UDXXXThe CMOVcc instruction is not supported, as indicated byEDX bit 15 of CPUID function 0000_0001h or function8000_0001h.Stack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceCMOVcc93AMD64 Technology24594—Rev.
3.13—July 2007CMPCompareCompares the contents of a register or memory location (first operand) with an immediate value or thecontents of a register or memory location (second operand), and sets or clears the status flags in therFLAGS register to reflect the results. To perform the comparison, the instruction subtracts the secondoperand from the first operand and sets the status flags in the same manner as the SUB instruction, butdoes not alter the first operand. If the second operand is an immediate value, the instruction signextends the value to the length of the first operand.Use the CMP instruction to set the condition codes for a subsequent conditional jump (Jcc),conditional move (CMOVcc), or conditional SETcc instruction. Appendix E, “Instruction Effects onRFLAGS,” shows how instructions affect the rFLAGS status flags..MnemonicOpcodeDescriptionCMP AL, imm83C ibCompare an 8-bit immediate value with the contents ofthe AL register.CMP AX, imm163D iwCompare a 16-bit immediate value with the contents ofthe AX register.CMP EAX, imm323D idCompare a 32-bit immediate value with the contents ofthe EAX register.CMP RAX, imm323D idCompare a 32-bit immediate value with the contents ofthe RAX register.CMP reg/mem8, imm880 /7 ibCompare an 8-bit immediate value with the contents ofan 8-bit register or memory operand.CMP reg/mem16, imm1681 /7 iwCompare a 16-bit immediate value with the contents ofa 16-bit register or memory operand.CMP reg/mem32, imm3281 /7 idCompare a 32-bit immediate value with the contents ofa 32-bit register or memory operand.CMP reg/mem64, imm3281 /7 idCompare a 32-bit signed immediate value with thecontents of a 64-bit register or memory operand.CMP reg/mem16, imm883 /7 ibCompare an 8-bit signed immediate value with thecontents of a 16-bit register or memory operand.CMP reg/mem32, imm883 /7 ibCompare an 8-bit signed immediate value with thecontents of a 32-bit register or memory operand.CMP reg/mem64, imm883 /7 ibCompare an 8-bit signed immediate value with thecontents of a 64-bit register or memory operand.CMP reg/mem8, reg838 /rCompare the contents of an 8-bit register or memoryoperand with the contents of an 8-bit register.CMP reg/mem16, reg1639 /rCompare the contents of a 16-bit register or memoryoperand with the contents of a 16-bit register.CMP reg/mem32, reg3239 /rCompare the contents of a 32-bit register or memoryoperand with the contents of a 32-bit register.CMP reg/mem64, reg6439 /rCompare the contents of a 64-bit register or memoryoperand with the contents of a 64-bit register.94CMPInstruction Reference24594—Rev.
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