Volume 3 General-Purpose and System Instructions (794097), страница 24
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3.13—July 2007AMD64 TechnologyDIVUnsigned DivideDivides the unsigned value in a register by the unsigned value in the specified register or memorylocation. The register to be divided depends on the size of the divisor.When dividing a word, the dividend is in the AX register. The instruction stores the quotient in the ALregister and the remainder in the AH register.When dividing a doubleword, quadword, or double quadword, the most-significant word of thedividend is in the rDX register and the least-significant word is in the rAX register. After the division,the instruction stores the quotient in the rAX register and the remainder in the rDX register.The following table summarizes the action of this instruction:Division SizeDividendDivisorQuotientRemainderMaximum QuotientAXreg/mem8ALAH255DX:AXreg/mem16AXDX65,535Quadword/doublewordEDX:EAXreg/mem32EAXEDX2 32 – 1Double quadword/quadwordRDX:RAXreg/mem64RAXRDX264 – 1Word/byteDoubleword/wordThe instruction truncates non-integral results towards 0 and the remainder is always less than thedivisor.
An overflow generates a #DE (divide error) exception, rather than setting the CF flag.Division by zero generates a divide-by-zero exception.MnemonicOpcodeDescriptionDIV reg/mem8F6 /6Perform unsigned division of AX by the contents of an 8bit register or memory location and store the quotient inAL and the remainder in AH.DIV reg/mem16F7 /6Perform unsigned division of DX:AX by the contents of a16-bit register or memory operand store the quotient inAX and the remainder in DX.DIV reg/mem32F7 /6Perform unsigned division of EDX:EAX by the contentsof a 32-bit register or memory location and store thequotient in EAX and the remainder in EDX.DIV reg/mem64F7 /6Perform unsigned division of RDX:RAX by the contentsof a 64-bit register or memory location and store thequotient in RAX and the remainder in RDX.Related InstructionsMULInstruction ReferenceDIV109AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFUUUUU76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionXXXThe divisor operand was 0.XXXThe quotient was too large for the designated register.Stack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Divide by zero, #DEPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.110DIVInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyENTERCreate Procedure Stack FrameCreates a stack frame for a procedure.The first operand specifies the size of the stack frame allocated by the instruction.The second operand specifies the nesting level (0 to 31—the value is automatically masked to 5 bits).For nesting levels of 1 or greater, the processor copies earlier stack frame pointers before adjusting thestack pointer. This action provides a called procedure with access points to other nested stack frames.The 32-bit enter N, 0 (a nesting level of 0) instruction is equivalent to the following 32-bitinstruction sequence:pushmovsubebpebp, espesp, N; save current EBP; set stack frame pointer value; allocate space for local variablesThe ENTER and LEAVE instructions provide support for block structured languages. The LEAVEinstruction releases the stack frame on returning from a procedure.In 64-bit mode, the operand size of ENTER defaults to 64 bits, and there is no prefix available forencoding a 32-bit operand size.MnemonicOpcodeDescriptionENTER imm16, 0C8 iw 00Create a procedure stack frame.ENTER imm16, 1C8 iw 01Create a nested stack frame for a procedure.ENTER imm16, imm8C8 iw ibCreate a nested stack frame for a procedure.Action// See “Pseudocode Definitions” on page 41.ENTER_START:temp_ALLOC_SPACE = word-sized immediate specified in the instruction(first operand), zero-extended to 64 bitstemp_LEVEL = byte-sized immediate specified in the instruction(second operand), zero-extended to 64 bitstemp_LEVEL = temp_LEVEL AND 0x1f// only keep 5 bits of level countPUSH.v old_RBPtemp_RBP = RSP// This value of RSP will eventually be loaded// into RBP.// Push "temp_LEVEL" parameters to the stack.IF (temp_LEVEL>0){FOR (I=1; I<temp_LEVEL; I++)Instruction ReferenceENTER111AMD64 Technology24594—Rev.
3.13—July 2007// All but one of the parameters are copied// from higher up on the stack.{temp_DATA = READ_MEM.v [SS:old_RBP-I*V]PUSH.v temp_DATA}PUSH.v temp_RBP// The last parameter is the offset of the old// value of RSP on the stack.}RSP.s = RSP - temp_ALLOC_SPACE// Leave "temp_ALLOC_SPACE" free bytes on// the stackWRITE_MEM.v [SS:RSP.s] = temp_unused// ENTER finishes with a memory write// check on the final stack pointer,// but no write actually occurs.RBP.v = temp_RBPEXITRelated InstructionsLEAVErFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionXXA memory address exceeded the stack-segment limit or wasnon-canonical.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Stack, #SS112XENTERInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyIDIVSigned DivideDivides the signed value in a register by the signed value in the specified register or memory location.The register to be divided depends on the size of the divisor.When dividing a word, the dividend is in the AX register.
The instruction stores the quotient in the ALregister and the remainder in the AH register.When dividing a doubleword, quadword, or double quadword, the most-significant word of thedividend is in the rDX register and the least-significant word is in the rAX register. After the division,the instruction stores the quotient in the rAX register and the remainder in the rDX register.The following table summarizes the action of this instruction:Division SizeDividendDivisorQuotientRemainderQuotient RangeAXreg/mem8ALAH–128 to +127DX:AXreg/mem16AXDX–32,768 to +32,767Quadword/doublewordEDX:EAXreg/mem32EAXEDX–2 31 to 2 31– 1Double quadword/quadwordRDX:RAXreg/mem64RAXRDX–2 63 to 263– 1Word/byteDoubleword/wordThe instruction truncates non-integral results towards 0.
The sign of the remainder is always the sameas the sign of the dividend, and the absolute value of the remainder is less than the absolute value of thedivisor. An overflow generates a #DE (divide error) exception, rather than setting the OF flag.To avoid overflow problems, precede this instruction with a CBW, CWD, CDQ, or CQO instruction tosign-extend the dividend.MnemonicOpcodeDescriptionIDIV reg/mem8F6 /7Perform signed division of AX by the contents of an 8-bitregister or memory location and store the quotient in ALand the remainder in AH.IDIV reg/mem16F7 /7Perform signed division of DX:AX by the contents of a16-bit register or memory location and store the quotientin AX and the remainder in DX.IDIV reg/mem32F7 /7Perform signed division of EDX:EAX by the contents ofa 32-bit register or memory location and store thequotient in EAX and the remainder in EDX.IDIV reg/mem64F7 /7Perform signed division of RDX:RAX by the contents ofa 64-bit register or memory location and store thequotient in RAX and the remainder in RDX.Instruction ReferenceIDIV113AMD64 Technology24594—Rev.
3.13—July 2007Related InstructionsIMULrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFUUUUU76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionXXXThe divisor operand was 0.XXXThe quotient was too large for the designated register.Stack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Divide by zero, #DEPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.114IDIVInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyIMULSigned MultiplyMultiplies two signed operands. The number of operands determines the form of the instruction.If a single operand is specified, the instruction multiplies the value in the specified general-purposeregister or memory location by the value in the AL, AX, EAX, or RAX register (depending on theoperand size) and stores the product in AX, DX:AX, EDX:EAX, or RDX:RAX, respectively.If two operands are specified, the instruction multiplies the value in a general-purpose register (firstoperand) by an immediate value or the value in a general-purpose register or memory location (secondoperand) and stores the product in the first operand location.If three operands are specified, the instruction multiplies the value in a general-purpose register ormemory location (second operand), by an immediate value (third operand) and stores the product in aregister (first operand).The IMUL instruction sign-extends an immediate operand to the length of the other register/memoryoperand.The CF and OF flags are set if, due to integer overflow, the double-width multiplication result cannotbe represented in the half-width destination register.
Otherwise the CF and OF flags are cleared.MnemonicOpcodeDescriptionIMUL reg/mem8F6 /5Multiply the contents of AL by the contents of an 8-bitmemory or register operand and put the signed result inAX.IMUL reg/mem16F7 /5Multiply the contents of AX by the contents of a 16-bitmemory or register operand and put the signed result inDX:AX.IMUL reg/mem32F7 /5Multiply the contents of EAX by the contents of a 32-bitmemory or register operand and put the signed result inEDX:EAX.IMUL reg/mem64F7 /5Multiply the contents of RAX by the contents of a 64-bitmemory or register operand and put the signed result inRDX:RAX.IMUL reg16, reg/mem160F AF /rMultiply the contents of a 16-bit destination register bythe contents of a 16-bit register or memory operand andput the signed result in the 16-bit destination register.IMUL reg32, reg/mem320F AF /rMultiply the contents of a 32-bit destination register bythe contents of a 32-bit register or memory operand andput the signed result in the 32-bit destination register.IMUL reg64, reg/mem640F AF /rMultiply the contents of a 64-bit destination register bythe contents of a 64-bit register or memory operand andput the signed result in the 64-bit destination register.IMUL reg16, reg/mem16, imm86B /r ibMultiply the contents of a 16-bit register or memoryoperand by a sign-extended immediate byte and put thesigned result in the 16-bit destination register.Instruction ReferenceIMUL115AMD64 Technology24594—Rev.
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