Volume 3 General-Purpose and System Instructions (794097), страница 22
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3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionCMP reg8, reg/mem83A /rCompare the contents of an 8-bit register with thecontents of an 8-bit register or memory operand.CMP reg16, reg/mem163B /rCompare the contents of a 16-bit register with thecontents of a 16-bit register or memory operand.CMP reg32, reg/mem323B /rCompare the contents of a 32-bit register with thecontents of a 32-bit register or memory operand.CMP reg64, reg/mem643B /rCompare the contents of a 64-bit register with thecontents of a 64-bit register or memory operand.When interpreting operands as unsigned, flag settings are as follows:OperandsCFZFdest > source00dest = source01dest < source10When interpreting operands as signed, flag settings are as follows:OperandsOFZFdest > sourceSF0dest = source01dest < sourceNOT SF0Related InstructionsSUB, CMPSx, SCASxInstruction ReferenceCMP95AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.96CMPInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyCMPSCMPSBCMPSWCMPSDCMPSQCompare StringsCompares the bytes, words, doublewords, or quadwords pointed to by the rSI and rDI registers, sets orclears the status flags of the rFLAGS register to reflect the results, and then increments or decrementsthe rSI and rDI registers according to the state of the DF flag in the rFLAGS register. To perform thecomparison, the instruction subtracts the second operand from the first operand and sets the statusflags in the same manner as the SUB instruction, but does not alter the first operand.
The two operandsmust be the same size.If the DF flag is 0, the instruction increments rSI and rDI; otherwise, it decrements the pointers. Itincrements or decrements the pointers by 1, 2, 4, or 8, depending on the size of the operands.The forms of the CMPSx instruction with explicit operands address the first operand at seg:[rSI]. Thevalue of seg defaults to the DS segment, but may be overridden by a segment prefix. These instructionsalways address the second operand at ES:[rDI]. ES may not be overridden. The explicit operands serveonly to specify the type (size) of the values being compared and the segment used by the first operand.The no-operands forms of the instruction use the DS:[rSI] and ES:[rDI] registers to point to the valuesto be compared. The mnemonic determines the size of the operands.Do not confuse this CMPSD instruction with the same-mnemonic CMPSD (compare scalar doubleprecision floating-point) instruction in the 128-bit media instruction set.
Assemblers can distinguishthe instructions by the number and type of operands.For block comparisons, the CMPS instruction supports the REPE or REPZ prefixes (they aresynonyms) and the REPNE or REPNZ prefixes (they are synonyms). For details about the REPprefixes, see “Repeat Prefixes” on page 9. If a conditional jump instruction like JL follows a CMPSxinstruction, the jump occurs if the value of the seg:[rSI] operand is less than the ES:[rDI] operand.
Thisaction allows lexicographical comparisons of string or array elements. A CMPSx instruction can alsooperate inside a loop controlled by the LOOPcc instruction.MnemonicOpcodeDescriptionCMPS mem8, mem8A6Compare the byte at DS:rSI with the byte at ES:rDI andthen increment or decrement rSI and rDI.CMPS mem16, mem16A7Compare the word at DS:rSI with the word at ES:rDI andthen increment or decrement rSI and rDI.CMPS mem32, mem32A7Compare the doubleword at DS:rSI with the doublewordat ES:rDI and then increment or decrement rSI and rDI.CMPS mem64, mem64A7Compare the quadword at DS:rSI with the quadword atES:rDI and then increment or decrement rSI and rDI.Instruction ReferenceCMPSx97AMD64 Technology24594—Rev. 3.13—July 2007MnemonicOpcodeDescriptionCMPSBA6Compare the byte at DS:rSI with the byte at ES:rDI andthen increment or decrement rSI and rDI.CMPSWA7Compare the word at DS:rSI with the word at ES:rDI andthen increment or decrement rSI and rDI.CMPSDA7Compare the doubleword at DS:rSI with the doublewordat ES:rDI and then increment or decrement rSI and rDI.CMPSQA7Compare the quadword at DS:rSI with the quadword atES:rDI and then increment or decrement rSI and rDI.Related InstructionsCMP, SCASxrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.98CMPSxInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyCMPXCHGCompare and ExchangeCompares the value in the AL, AX, EAX, or RAX register with the value in a register or a memorylocation (first operand). If the two values are equal, the instruction copies the value in the secondoperand to the first operand and sets the ZF flag in the rFLAGS register to 1. Otherwise, it copies thevalue in the first operand to the AL, AX, EAX, or RAX register and clears the ZF flag to 0.The OF, SF, AF, PF, and CF flags are set to reflect the results of the compare.When the first operand is a memory operand, CMPXCHG always does a read-modify-write on thememory operand.
If the compared operands were unequal, CMPXCHG writes the same value to thememory operand that was read.The forms of the CMPXCHG instruction that write to memory support the LOCK prefix. For detailsabout the LOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionCMPXCHG reg/mem8, reg80F B0 /rCompare AL register with an 8-bit register or memorylocation.
If equal, copy the second operand to the firstoperand. Otherwise, copy the first operand to AL.CMPXCHG reg/mem16, reg160F B1 /rCompare AX register with a 16-bit register or memorylocation. If equal, copy the second operand to the firstoperand. Otherwise, copy the first operand to AX.CMPXCHG reg/mem32, reg320F B1 /rCompare EAX register with a 32-bit register or memorylocation. If equal, copy the second operand to the firstoperand. Otherwise, copy the first operand to EAX.CMPXCHG reg/mem64, reg640F B1 /rCompare RAX register with a 64-bit register or memorylocation.
If equal, copy the second operand to the firstoperand. Otherwise, copy the first operand to RAX.Related InstructionsCMPXCHG8B, CMPXCHG16BInstruction ReferenceCMPXCHG99AMD64 Technology24594—Rev. 3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.100CMPXCHGInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyCMPXCHG8BCMPXCHG16BCompare and Exchange Eight BytesCompare and Exchange Sixteen BytesCompares the value in the rDX:rAX registers with a 64-bit or 128-bit value in the specified memorylocation. If the values are equal, the instruction copies the value in the rCX:rBX registers to thememory location and sets the zero flag (ZF) of the rFLAGS register to 1. Otherwise, it copies the valuein memory to the rDX:rAX registers and clears ZF to 0.If the effective operand size is 16-bit or 32-bit, the CMPXCHG8B instruction is used.
This instructionuses the EDX:EAX and ECX:EBX register operands and a 64-bit memory operand. If the effectiveoperand size is 64-bit, the CMPXCHG16B instruction is used; this instruction uses RDX:RAX andRCX:RBX register operands and a 128-bit memory operand.The CMPXCHG8B and CMPXCHG16B instructions always do a read-modify-write on the memoryoperand. If the compared operands were unequal, the instructions write the same value to the memoryoperand that was read.The CMPXCHG8B and CMPXCHG16B instructions support the LOCK prefix.
For details about theLOCK prefix, see “Lock Prefix” on page 8.Support for the CMPXCHG8B and CMPXCHG16B instructions depends on the processorimplementation. To find out if a processor can execute the CMPXCHG8B instruction, use the CPUIDinstruction to determine whether EDX bit 8 of CPUID function 0000_0001h or function 8000_0001his set to 1. To find out if a processor can execute the CMPXCHG16B instruction, use the CPUIDinstruction to determine whether ECX bit 13 of CPUID function 0000_0001h is set to 1.The memory operand used by CMPXCHG16B must be 16-byte aligned or else a general-protectionexception is generated.MnemonicCMPXCHG8B mem64CMPXCHG16B mem128OpcodeDescription0F C7 /1 m64Compare EDX:EAX register to 64-bit memory location.If equal, set the zero flag (ZF) to 1 and copy theECX:EBX register to the memory location.
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