Volume 3 General-Purpose and System Instructions (794097), страница 26
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3.13—July 2007AMD64 TechnologyRIP = temp_RIPEXITINT_N_PROTECTED:temp_int_n_vector = byte-sized interrupt vector specified in the instruction,zero-extended to 64 bitstemp_idt_desc = READ_IDT (temp_int_n_vector)IF (temp_idt_desc.attr.type = ’taskgate’)TASK_SWITCH// using tss selector in the task gate as the target tssIF (LONG_MODE)// The size of the gate controls the size of the// stack pushes.V=8-byte// Long mode only uses 64-bit gates.ELSIF ((temp_idt_desc.attr.type = ’intgate32’)|| (temp_idt_desc.attr.type = ’trapgate32’))V=4-byte// Legacy mode, using a 32-bit gateELSE // gate is intgate16 or trapgate16V=2-byte// Legacy mode, using a 16-bit gatetemp_RIP = temp_idt_desc.offsetIF (LONG_MODE)// In long mode, we need to read the 2nd half of a// 16-byte interrupt-gate from the IDT, to get the// upper 32 bits of the target RIP{temp_upper = READ_MEM.q [idt:temp_int_n_vector*16+8]temp_RIP = tempRIP + (temp_upper SHL 32) // concatenate both halves of RIP}CS = READ_DESCRIPTOR (temp_idt_desc.segment, intcs_chk)IF (CS.attr.conforming=1)temp_CPL = CPLELSEtemp_CPL = CS.attr.dplIF (CPL=temp_CPL)// no privilege-level change{IF (LONG_MODE){IF (temp_idt_desc.ist!=0)// In long mode, if the IDT gate specifies an IST pointer,// a stack-switch is always doneRSP = READ_MEM.q [tss:ist_index*8+28]RSP = RSP AND 0xFFFFFFFFFFFFFFF0Instruction ReferenceINT123AMD64 Technology24594—Rev.
3.13—July 2007// In long mode, interrupts/exceptions align RSP to a// 16-byte boundaryPUSH.q old_SSPUSH.q old_RSP// In long mode, SS:RSP is always pushed to the stack}PUSH.v old_RFLAGSPUSH.v old_CSPUSH.v next_RIPIF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit))EXCEPTION [#GP(0)]RFLAGS.VM,NT,TF,RF clearedRFLAGS.IF cleared if interrupt gateRIP = temp_RIPEXIT}ELSE // (CPL > temp_CPL), changing privilege level{CPL = temp_CPLtemp_SS_desc:temp_RSP = READ_INNER_LEVEL_STACK_POINTER(CPL, temp_idt_desc.ist)IF (LONG_MODE)temp_RSP = temp_RSP AND 0xFFFFFFFFFFFFFFF0// in long mode, interrupts/exceptions align rsp// to a 16-byte boundaryRSP.q = temp_RSPSS = temp_SS_descPUSH.vPUSH.vPUSH.vPUSH.vPUSH.vold_SS // #SS on the following pushes uses SS.sel as error codeold_RSPold_RFLAGSold_CSnext_RIPIF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit))EXCEPTION [#GP(0)]RFLAGS.VM,NT,TF,RF clearedRFLAGS.IF cleared if interrupt gateRIP = temp_RIPEXIT}124INTInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyINT_N_VIRTUAL:temp_int_n_vector = byte-sized interrupt vector specified in the instruction,zero-extended to 64 bitsIF (CR4.VME=0)// vme isn’t enabled{IF (RFLAGS.IOPL=3)INT_N_VIRTUAL_TO_PROTECTEDELSEEXCEPTION [#GP(0)]}temp_IRB_BASE = READ_MEM.w [tss:102] - 32// check the vme Int-n Redirection Bitmap (IRB), to see// if we should redirect this interrupt to a virtual-mode// handlertemp_VME_REDIRECTION_BIT = READ_BIT_ARRAY ([tss:temp_IRB_BASE],temp_int_n_vector)IF (temp_VME_REDIRECTION_BIT=1){// the virtual-mode int-n bitmap bit is set, so don’t// redirect this interruptIF (RFLAGS.IOPL=3)INT_N_VIRTUAL_TO_PROTECTEDELSEEXCEPTION [#GP(0)]}ELSE// redirect interrupt through virtual-mode idt{temp_RIP = READ_MEM.w [0:temp_int_n_vector*4]// read target CS:RIP from the virtual-mode idt at// linear address 0temp_CS = READ_MEM.w [0:temp_int_n_vector*4+2]IF (RFLAGS.IOPL < 3)old_RFLAGS = old_RFLAGS with VIF bit shifted into IF bit, and IOPL = 3PUSH.w old_RFLAGSPUSH.w old_CSPUSH.w next_RIPCS.sel = temp_CSCS.base = temp_CS SHL 4RFLAGS.TF,RF clearedRIP = temp_RIP// RFLAGS.IF cleared if IOPL = 3// RFLAGS.VIF cleared if IOPL < 3EXIT}Instruction ReferenceINT125AMD64 Technology24594—Rev.
3.13—July 2007INT_N_VIRTUAL_TO_PROTECTED:temp_idt_desc = READ_IDT (temp_int_n_vector)IF (temp_idt_desc.attr.type = ’taskgate’)TASK_SWITCH // using tss selector in the task gate as the target tssIF ((temp_idt_desc.attr.type = ’intgate32’)|| (temp_idt_desc.attr.type = ’trapgate32’))// the size of the gate controls the size of the stack pushesV=4-byte// legacy mode, using a 32-bit gateELSE // gate is intgate16 or trapgate16V=2-byte// legacy mode, using a 16-bit gatetemp_RIP = temp_idt_desc.offsetCS = READ_DESCRIPTOR (temp_idt_desc.segment, intcs_chk)IF (CS.attr.dpl!=0)// Handler must run at CPL 0.EXCEPTION [#GP(CS.sel)]CPL = 0temp_ist = 0// Legacy mode doesn’t use ist pointerstemp_SS_desc:temp_RSP = READ_INNER_LEVEL_STACK_POINTER (CPL, temp_ist)RSP.q = temp_RSPSS = temp_SS_descPUSH.vPUSH.vPUSH.vPUSH.vPUSH.vPUSH.vPUSH.vPUSH.vPUSH.vold_GSold_FSold_DSold_ESold_SSold_RSPold_RFLAGSold_CSnext_RIP// #SS on the following pushes use SS.sel as error code.// Pushed with RF clear.IF (temp_RIP > CS.limit)EXCEPTION [#GP(0)]DSESFSGS====NULLNULLNULLNULL////////can’tcan’tcan’tcan’tuseuseuseusevirtual-modevirtual-modevirtual-modevirtual-modeselectorsselectorsselectorsselectorsininininprotectedprotectedprotectedprotectedmodemodemodemodeRFLAGS.VM,NT,TF,RF clearedRFLAGS.IF cleared if interrupt gateRIP = temp_RIPEXIT126INTInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyRelated InstructionsINT 3, INTO, BOUNDrFLAGS AffectedIf a task switch occurs, all flags are modified. Otherwise settings are as follows:ID21VIP20VIFACVMRFNTMMM0M1918171614IOPL13–12OF11DF10IFTFM098SFZFAFPFCF76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedInvalid TSS, #TS(selector)Segment notpresent, #NP(selector)Stack, #SSXStack, #SS(selector)Instruction ReferenceCause of ExceptionXXAs part of a stack switch, the target stack segment selector orrSP in the TSS was beyond the TSS limit.XXAs part of a stack switch, the target stack segment selector inthe TSS was a null selector.XXAs part of a stack switch, the target stack segment selector’sTI bit was set, but the LDT selector was a null selector.XXAs part of a stack switch, the target stack segment selector inthe TSS was beyond the limit of the GDT or LDT descriptortable.XXAs part of a stack switch, the target stack segment selector inthe TSS contained a RPL that was not equal to its DPL.XXAs part of a stack switch, the target stack segment selector inthe TSS contained a DPL that was not equal to the CPL of thecode segment selector.XXAs part of a stack switch, the target stack segment selector inthe TSS was not a writable segment.XXThe accessed code segment, interrupt gate, trap gate, taskgate, or TSS was not present.XXA memory address exceeded the stack segment limit or wasnon-canonical, and no stack switch occurred.XXAfter a stack switch, a memory address exceeded the stacksegment limit or was non-canonical.XXAs part of a stack switch, the SS register was loaded with anon-null segment selector and the segment was marked notpresent.INT127AMD64 TechnologyExceptionGeneral protection,#GP24594—Rev.
3.13—July 2007VirtualReal 8086 ProtectedXXXA memory address exceeded a data segment limit or was noncanonical.XXXThe target offset exceeded the code segment limit or was noncanonical.XGeneral protection,#GP(selector)Cause of ExceptionXThe IOPL was less than 3 and CR4.VME was 0.XIOPL was less than 3, CR4.VME was 1, and thecorresponding bit in the VME interrupt redirection bitmap was1.XXThe interrupt vector was beyond the limit of IDT.XXThe descriptor in the IDT was not an interrupt, trap, or taskgate in legacy mode or not a 64-bit interrupt or trap gate inlong mode.XXThe DPL of the interrupt, trap, or task gate descriptor was lessthan the CPL.XXThe segment selector specified by the interrupt or trap gatehad its TI bit set, but the LDT selector was a null selector.XXThe segment descriptor specified by the interrupt or trap gateexceeded the descriptor table limit or was a null selector.XXThe segment descriptor specified by the interrupt or trap gatewas not a code segment in legacy mode, or not a 64-bit codesegment in long mode.XThe DPL of the segment specified by the interrupt or trap gatewas greater than the CPL.The DPL of the segment specified by the interrupt or trap gatepointed was not 0 or it was a conforming segment.XPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.128INTInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyINTOInterrupt to Overflow VectorChecks the overflow flag (OF) in the rFLAGS register and calls the overflow exception (#OF) handlerif the OF flag is set to 1. This instruction has no effect if the OF flag is cleared to 0. The INTOinstruction detects overflow in signed number addition. See AMD64 Architecture Programmer’sManual Volume 1: Application Programming for more information on the OF flag.Using this instruction in 64-bit mode generates an invalid-opcode exception.For detailed descriptions of the steps performed by INT instructions, see the following:••Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” in Volume 2.Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in Volume 2.MnemonicOpcodeINTODescriptionCall overflow exception if the overflow flag is set.(Invalid in 64-bit mode.)CEActionIF (64BIT_MODE)EXCEPTION[#UD]IF (RFLAGS.OF = 1)EXCEPTION [#OF]EXIT// #OF is a trap, and pushes the rIP of the instruction// following INTO.Related InstructionsINT, INT 3, BOUNDrFLAGS AffectedNone.ExceptionsExceptionOverflow, #OFVirtualReal 8086 ProtectedXInvalid opcode, #UDInstruction ReferenceXCause of ExceptionXThe INTO instruction was executed with 0F set to 1.XInstruction was executed in 64-bit mode.INTO129AMD64 Technology24594—Rev.
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