Volume 3 General-Purpose and System Instructions (794097), страница 30
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3.13—July 2007rFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GP152VirtualReal 8086 ProtectedXXXCause of ExceptionThe target offset exceeded the code segment limit or was noncanonical.LOOPccInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyLZCNTCount Leading ZerosCounts the number of leading zero bits in the 16-, 32-, or 64-bit general purpose register or memorysource operand. Counting starts downward from the most significant bit and stops when the highest bithaving a value of 1 is encountered or when the least significant bit is encountered. The count is writtento the destination register.If the input operand is zero, CF is set to 1 and the size (in bits) of the input operand is written to thedestination register. Otherwise, CF is cleared.If the most significant bit is a one, the ZF flag is set to 1, zero is written to the destination register.Otherwise, ZF is cleared.Support for the LZCNT instruction is indicated by ECX bit 5 (LZCNT) as returned by CPUIDfunction 8000_0001h.
If the LZCNT instruction is not available, the encoding is treated as the BSRinstruction. Software MUST check the CPUID bit once per program or library initialization beforeusing the LZCNT instruction, or inconsistent behavior may result.MnemonicOpcodeDescriptionLZCNTreg16, reg/mem16F3 0F BD /rCount the number of leading zeros in reg/mem16.LZCNTreg32, reg/mem32F3 0F BD /rCount the number of leading zeros in reg/mem32.LZCNTreg64, reg/mem64F3 0F BD /rCount the number of leading zeros in reg/mem64.Related InstructionsBSF, BSR, POPCNTInstruction ReferenceLZCNT153AMD64 Technology24594—Rev. 3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFU2120191817161413–12111098SFZFAFPFCFUMUUM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSGeneral protection, #GPVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit orwas non-canonical.XXXA memory address exceeded a data segment limit or wasnon-canonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.154LZCNTInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyMFENCEMemory FenceActs as a barrier to force strong memory ordering (serialization) between load and store instructionspreceding the MFENCE, and load and store instructions that follow the MFENCE. The processor mayperform loads out of program order with respect to non-conflicting stores for certain memory types.The MFENCE instruction guarantees that the system completes all previous memory accesses beforeexecuting subsequent accesses.The MFENCE instruction is weakly-ordered with respect to data and instruction prefetches.Speculative loads initiated by the processor, or specified explicitly using cache-prefetch instructions,can be reordered around an MFENCE.In addition to load and store instructions, the MFENCE instruction is strongly ordered with respect toother MFENCE instructions, LFENCE instructions, SFENCE instructions, serializing instructions,and CLFLUSH instructions.
Further details on the use of MFENCE to order accesses among differingmemory types may be found in AMD64 Architecture Programmer’s Manual Volume 2: SystemProgramming, section 7.4 “Memory Types” on page 168.Support for the MFENCE instruction is indicated when the SSE2 bit (bit 26) is set to 1 in EDX afterexecuting CPUID with function 0000_0001h.MnemonicOpcodeMFENCE0F AE F0DescriptionForce strong ordering of (serialized) load and storeoperations.Related InstructionsLFENCE, SFENCErFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXInstruction ReferenceXXCause of ExceptionThe MFENCE instruction is not supported as indicated by bit26 of CPUID function 0000_0001h.MFENCE155AMD64 Technology24594—Rev. 3.13—July 2007MOVMoveCopies an immediate value or the value in a general-purpose register, segment register, or memorylocation (second operand) to a general-purpose register, segment register, or memory location.
Thesource and destination must be the same size (byte, word, doubleword, or quadword) and cannot bothbe memory locations.In opcodes A0 through A3, the memory offsets (called moffsets) are address sized. In 64-bit mode,memory offsets default to 64 bits. Opcodes A0–A3, in 64-bit mode, are the only cases that support a64-bit offset value. (In all other cases, offsets and displacements are a maximum of 32 bits.) The B8through BF (B8 +rq) opcodes, in 64-bit mode, are the only cases that support a 64-bit immediate value(in all other cases, immediate values are a maximum of 32 bits).When reading segment-registers with a 32-bit operand size, the processor zero-extends the 16-bitselector results to 32 bits. When reading segment-registers with a 64-bit operand size, the processorzero-extends the 16-bit selector to 64 bits.
If the destination operand specifies a segment register (DS,ES, FS, GS, or SS), the source operand must be a valid segment selector.It is possible to move a null segment selector value (0000–0003h) into the DS, ES, FS, or GS register.This action does not cause a general protection fault, but a subsequent reference to such a segmentdoes cause a #GP exception. For more information about segment selectors, see “Segment Selectorsand Registers” on page 67.When the MOV instruction is used to load the SS register, the processor blocks external interrupts untilafter the execution of the following instruction. This action allows the following instruction to be aMOV instruction to load a stack pointer into the ESP register (MOV ESP,val) before an interruptoccurs.
However, the LSS instruction provides a more efficient method of loading SS and ESP.Attempting to use the MOV instruction to load the CS register generates an invalid opcode exception(#UD). Use the far JMP, CALL, or RET instructions to load the CS register.To initialize a register to 0, rather than using a MOV instruction, it may be more efficient to use theXOR instruction with identical destination and source operands.MnemonicOpcodeDescriptionMOV reg/mem8, reg888 /rMove the contents of an 8-bit register to an 8-bitdestination register or memory operand.MOV reg/mem16, reg1689 /rMove the contents of a 16-bit register to a 16-bitdestination register or memory operand.MOV reg/mem32, reg3289 /rMove the contents of a 32-bit register to a 32-bitdestination register or memory operand.MOV reg/mem64, reg6489 /rMove the contents of a 64-bit register to a 64-bitdestination register or memory operand.MOV reg8, reg/mem88A /rMove the contents of an 8-bit register or memoryoperand to an 8-bit destination register.156MOVInstruction Reference24594—Rev.
3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionMOV reg16, reg/mem168B /rMove the contents of a 16-bit register or memoryoperand to a 16-bit destination register.MOV reg32, reg/mem328B /rMove the contents of a 32-bit register or memoryoperand to a 32-bit destination register.MOV reg64, reg/mem648B /rMove the contents of a 64-bit register or memoryoperand to a 64-bit destination register.MOV reg16/32/64/mem16,segReg8C /rMove the contents of a segment register to a 16-bit, 32bit, or 64-bit destination register or to a 16-bit memoryoperand.MOV segReg, reg/mem168E /rMove the contents of a 16-bit register or memoryoperand to a segment register.MOV AL, moffset8A0Move 8-bit data at a specified memory offset to the ALregister.MOV AX, moffset16A1Move 16-bit data at a specified memory offset to the AXregister.MOV EAX, moffset32A1Move 32-bit data at a specified memory offset to theEAX register.MOV RAX, moffset64A1Move 64-bit data at a specified memory offset to theRAX register.MOV moffset8, ALA2Move the contents of the AL register to an 8-bit memoryoffset.MOV moffset16, AXA3Move the contents of the AX register to a 16-bit memoryoffset.MOV moffset32, EAXA3Move the contents of the EAX register to a 32-bitmemory offset.MOV moffset64, RAXA3Move the contents of the RAX register to a 64-bitmemory offset.MOV reg8, imm8B0 +rb +ibMove an 8-bit immediate value into an 8-bit register.MOV reg16, imm16B8 +rw +iwMove a 16-bit immediate value into a 16-bit register.MOV reg32, imm32B8 +rd +idMove an 32-bit immediate value into a 32-bit register.MOV reg64, imm64B8 +rq +iqMove an 64-bit immediate value into a 64-bit register.MOV reg/mem8, imm8C6 /0 +ibMove an 8-bit immediate value to an 8-bit register ormemory operand.MOV reg/mem16, imm16C7 /0 +iwMove a 16-bit immediate value to a 16-bit register ormemory operand.MOV reg/mem32, imm32C7 /0 +idMove a 32-bit immediate value to a 32-bit register ormemory operand.MOV reg/mem64, imm32C7 /0 +idMove a 32-bit signed immediate value to a 64-bitregister or memory operand.Instruction ReferenceMOV157AMD64 Technology24594—Rev.
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