Volume 3 General-Purpose and System Instructions (794097), страница 25
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3.13—July 2007MnemonicOpcodeDescriptionIMUL reg32, reg/mem32, imm86B /r ibMultiply the contents of a 32-bit register or memoryoperand by a sign-extended immediate byte and put thesigned result in the 32-bit destination register.IMUL reg64, reg/mem64, imm86B /r ibMultiply the contents of a 64-bit register or memoryoperand by a sign-extended immediate byte and put thesigned result in the 64-bit destination register.IMUL reg16, reg/mem16,imm1669 /r iwMultiply the contents of a 16-bit register or memoryoperand by a sign-extended immediate word and put thesigned result in the 16-bit destination register.IMUL reg32, reg/mem32,imm3269 /r idMultiply the contents of a 32-bit register or memoryoperand by a sign-extended immediate double and putthe signed result in the 32-bit destination register.IMUL reg64, reg/mem64,imm3269 /r idMultiply the contents of a 64-bit register or memoryoperand by a sign-extended immediate double and putthe signed result in the 64-bit destination register.Related InstructionsIDIVrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFUUUUM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.116IMULInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyINInput from PortTransfers a byte, word, or doubleword from an I/O port (second operand) to the AL, AX or EAXregister (first operand).
The port address can be an 8-bit immediate value (00h to FFh) or contained inthe DX register (0000h to FFFFh).The port is in the processor’s I/O address space. For 8-bit I/O port accesses, the opcode determines theport size. For 16-bit and 32-bit accesses, the operand-size attribute determines the port size. If theoperand size is 64-bits, IN reads only 32 bits from the I/O port.If the CPL is higher than IOPL, or the mode is virtual mode, IN checks the I/O permission bitmap inthe TSS before allowing access to the I/O port. (See Volume 2 for details on the TSS I/O permissionbitmap.)MnemonicOpcodeDescriptionIN AL, imm8E4 ibInput a byte from the port at the address specified byimm8 and put it into the AL register.IN AX, imm8E5 ibInput a word from the port at the address specified byimm8 and put it into the AX register.IN EAX, imm8E5 ibInput a doubleword from the port at the addressspecified by imm8 and put it into the EAX register.IN AL, DXECInput a byte from the port at the address specified by theDX register and put it into the AL register.IN AX, DXEDInput a word from the port at the address specified bythe DX register and put it into the AX register.IN EAX, DXEDInput a doubleword from the port at the addressspecified by the DX register and put it into the EAXregister.Related InstructionsINSx, OUT, OUTSxrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedGeneral protection,#GPPage fault, #PFInstruction ReferenceOne or more I/O permission bits were set in the TSS for theaccessed port.XXCause of ExceptionXThe CPL was greater than the IOPL and one or more I/Opermission bits were set in the TSS for the accessed port.XA page fault resulted from the execution of the instruction.IN117AMD64 Technology24594—Rev.
3.13—July 2007INCIncrement by 1Adds 1 to the specified register or memory location. The CF flag is not affected, even if the operand isincremented to 0000.The one-byte forms of this instruction (opcodes 40 through 47) are used as REX prefixes in 64-bitmode. See “REX Prefixes” on page 11.The forms of the INC instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.To perform an increment operation that updates the CF flag, use an ADD instruction with animmediate operand of 1.MnemonicOpcodeDescriptionINC reg/mem8FE /0Increment the contents of an 8-bit register or memorylocation by 1.INC reg/mem16FF /0Increment the contents of a 16-bit register or memorylocation by 1.INC reg/mem32FF /0Increment the contents of a 32-bit register or memorylocation by 1.INC reg/mem64FF /0Increment the contents of a 64-bit register or memorylocation by 1.INC reg1640 +rwIncrement the contents of a 16-bit register by 1.(These opcodes are used as REX prefixes in 64-bitmode.
See “REX Prefixes” on page 11.)INC reg3240 +rdIncrement the contents of a 32-bit register by 1.(These opcodes are used as REX prefixes in 64-bitmode. See “REX Prefixes” on page 11.)Related InstructionsADD, DEC118INCInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFMMMM7642CF0Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceINC119AMD64 Technology24594—Rev.
3.13—July 2007INSINSBINSWINSDInput StringTransfers data from the I/O port specified in the DX register to an input buffer specified in the rDIregister and increments or decrements the rDI register according to the setting of the DF flag in therFLAGS register.If the DF flag is 0, the instruction increments rDI by 1, 2, or 4, depending on the number of bytes read.If the DF flag is 1, it decrements the pointer by 1, 2, or 4.In 16-bit and 32-bit mode, the INS instruction always uses ES as the data segment.
The ES segmentcannot be overridden with a segment override prefix. In 64-bit mode, INS always uses theunsegmented memory space.The INS instructions use the explicit memory operand (first operand) to determine the size of the I/Oport, but always use ES:[rDI] for the location of the input buffer. The explicit register operand (secondoperand) specifies the I/O port address and must always be DX.The INSB, INSW, and INSD instructions copy byte, word, and doubleword data, respectively, from theI/O port (0000h to FFFFh) specified in the DX register to the input buffer specified in the ES:rDIregisters.If the operand size is 64-bits, the instruction behaves as if the operand size were 32-bits.If the CPL is higher than the IOPL or the mode is virtual mode, INSx checks the I/O permission bitmapin the TSS before allowing access to the I/O port. (See volume 2 for details on the TSS I/O permissionbitmap.)The INSx instructions support the REP prefix for block input of rCX bytes, words, or doublewords.For details about the REP prefix, see “Repeat Prefixes” on page 9.MnemonicOpcodeDescriptionINS mem8, DX6CInput a byte from the port specified by DX, put it into thememory location specified in ES:rDI, and thenincrement or decrement rDI.INS mem16, DX6DInput a word from the port specified by DX register, put itinto the memory location specified in ES:rDI, and thenincrement or decrement rDI.INS mem32, DX6DInput a doubleword from the port specified by DX, put itinto the memory location specified in ES:rDI, and thenincrement or decrement rDI.INSB6CInput a byte from the port specified by DX, put it into thememory location specified in ES:rDI, and thenincrement or decrement rDI.120INSxInstruction Reference24594—Rev.
3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionINSW6DInput a word from the port specified by DX, put it into thememory location specified in ES:rDI, and thenincrement or decrement rDI.INSD6DInput a doubleword from the port specified by DX, put itinto the memory location specified in ES:rDI, and thenincrement or decrement rDI.Related InstructionsIN, OUT, OUTSxrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedXXXA memory address exceeded a data segment limit or was noncanonical.One or more I/O permission bits were set in the TSS for theaccessed port.XGeneral protection,#GPCause of ExceptionXThe CPL was greater than the IOPL and one or more I/Opermission bits were set in the TSS for the accessed port.XA null data segment was used to reference memory.XThe destination operand was in a non-writable segment.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceINSx121AMD64 Technology24594—Rev.
3.13—July 2007INTInterrupt to VectorTransfers execution to the interrupt handler specified by an 8-bit unsigned immediate value. This valueis an interrupt vector number (00h to FFh), which the processor uses as an index into the interruptdescriptor table (IDT).For detailed descriptions of the steps performed by INTn instructions, see the following:••Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” in Volume 2.Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in Volume 2.See also the descriptions of the INT3 instruction on page 259 and the INTO instruction on page 129.MnemonicOpcodeINT imm8CD ibDescriptionCall interrupt service routine specified by interruptvector imm8.Action// See “Pseudocode Definitions” on page 41.INT_N_START:IF (REAL_MODE)INT_N_REALELSIF (PROTECTED_MODE)INT_N_PROTECTEDELSE // (VIRTUAL_MODE)INT_N_VIRTUALINT_N_REAL:temp_int_n_vector = byte-sized interrupt vector specified in the instruction,zero-extended to 64 bitstemp_RIP = READ_MEM.w [idt:temp_int_n_vector*4]// read target CS:RIP from the real-mode idttemp_CS = READ_MEM.w [idt:temp_int_n_vector*4+2]PUSH.w old_RFLAGSPUSH.w old_CSPUSH.w next_RIPIF (temp_RIP>CS.limit)EXCEPTION [#GP]CS.sel = temp_CSCS.base = temp_CS SHL 4RFLAGS.AC,TF,IF,RF cleared122INTInstruction Reference24594—Rev.
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