Volume 3 General-Purpose and System Instructions (794097), страница 32
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3.13—July 2007MnemonicAMD64 TechnologyOpcodeDescriptionMOVSDA5Move doubleword at DS:rSI to ES:rDI, and thenincrement or decrement rSI and rDI.MOVSQA5Move quadword at DS:rSI to ES:rDI, and then incrementor decrement rSI and rDI.Related InstructionsMOV, LODSx, STOSxrFLAGS AffectedNoneExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVSx169AMD64 Technology24594—Rev.
3.13—July 2007MOVSXMove with Sign-ExtensionCopies the value in a register or memory location (second operand) into a register (first operand),extending the most significant bit of an 8-bit or 16-bit value into all higher bits in a 16-bit, 32-bit, or64-bit register.MnemonicOpcodeDescriptionMOVSX reg16, reg/mem80F BE /rMove the contents of an 8-bit register or memorylocation to a 16-bit register with sign extension.MOVSX reg32, reg/mem80F BE /rMove the contents of an 8-bit register or memorylocation to a 32-bit register with sign extension.MOVSX reg64, reg/mem80F BE /rMove the contents of an 8-bit register or memorylocation to a 64-bit register with sign extension.MOVSX reg32, reg/mem160F BF /rMove the contents of an 16-bit register or memorylocation to a 32-bit register with sign extension.MOVSX reg64, reg/mem160F BF /rMove the contents of an 16-bit register or memorylocation to a 64-bit register with sign extension.Related InstructionsMOVSXD, MOVZXrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.170MOVSXInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyMOVSXDMove with Sign-Extend DoublewordCopies the 32-bit value in a register or memory location (second operand) into a 64-bit register (firstoperand), extending the most significant bit of the 32-bit value into all higher bits of the 64-bit register.This instruction requires the REX prefix 64-bit operand size bit (REX.W) to be set to 1 to sign-extenda 32-bit source operand to a 64-bit result.
Without the REX operand-size prefix, the operand size willbe 32 bits, the default for 64-bit mode, and the source is zero-extended into a 64-bit register. With a 16bit operand size, only 16 bits are copied, without modifying the upper 48 bits in the destination.This instruction is available only in 64-bit mode. In legacy or compatibility mode this opcode isinterpreted as ARPL.MnemonicOpcodeMOVSXD reg64, reg/mem3263 /rDescriptionMove the contents of a 32-bit register or memoryoperand to a 64-bit register with sign extension.Related InstructionsMOVSX, MOVZXrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXA memory address was non-canonical.General protection,#GPXA memory address was non-canonical.Page fault, #PFXA page fault resulted from the execution of the instruction.Alignment check,#ACXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVSXD171AMD64 Technology24594—Rev.
3.13—July 2007MOVZXMove with Zero-ExtensionCopies the value in a register or memory location (second operand) into a register (first operand), zeroextending the value to fit in the destination register. The operand-size attribute determines the size ofthe zero-extended value.MnemonicOpcodeDescriptionMOVZX reg16, reg/mem80F B6 /rMove the contents of an 8-bit register or memoryoperand to a 16-bit register with zero-extension.MOVZX reg32, reg/mem80F B6 /rMove the contents of an 8-bit register or memoryoperand to a 32-bit register with zero-extension.MOVZX reg64, reg/mem80F B6 /rMove the contents of an 8-bit register or memoryoperand to a 64-bit register with zero-extension.MOVZX reg32, reg/mem160F B7 /rMove the contents of a 16-bit register or memoryoperand to a 32-bit register with zero-extension.MOVZX reg64, reg/mem160F B7 /rMove the contents of a 16-bit register or memoryoperand to a 64-bit register with zero-extension.Related InstructionsMOVSXD, MOVSXrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.172MOVZXInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyMULUnsigned MultiplyMultiplies the unsigned byte, word, doubleword, or quadword value in the specified register ormemory location by the value in AL, AX, EAX, or RAX and stores the result in AX, DX:AX,EDX:EAX, or RDX:RAX (depending on the operand size). It puts the high-order bits of the product inAH, DX, EDX, or RDX.If the upper half of the product is non-zero, the instruction sets the carry flag (CF) and overflow flag(OF) both to 1. Otherwise, it clears CF and OF to 0. The other arithmetic flags (SF, ZF, AF, PF) areundefined.MnemonicOpcodeDescriptionMUL reg/mem8F6 /4Multiplies an 8-bit register or memory operand by thecontents of the AL register and stores the result in theAX register.MUL reg/mem16F7 /4Multiplies a 16-bit register or memory operand by thecontents of the AX register and stores the result in theDX:AX register.MUL reg/mem32F7 /4Multiplies a 32-bit register or memory operand by thecontents of the EAX register and stores the result in theEDX:EAX register.MUL reg/mem64F7 /4Multiplies a 64-bit register or memory operand by thecontents of the RAX register and stores the result in theRDX:RAX register.Related InstructionsDIVrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFUUUUM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionStack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.Instruction ReferenceMUL173AMD64 TechnologyException24594—Rev. 3.13—July 2007VirtualReal 8086 ProtectedCause of ExceptionPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference is performed while alignmentchecking was enabled.174MULInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyNEGTwo’s Complement NegationPerforms the two’s complement negation of the value in the specified register or memory location bysubtracting the value from 0. Use this instruction only on signed integer numbers.If the value is 0, the instruction clears the CF flag to 0; otherwise, it sets CF to 1. The OF, SF, ZF, AF,and PF flag settings depend on the result of the operation.The forms of the NEG instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionNEG reg/mem8F6 /3Performs a two’s complement negation on an 8-bitregister or memory operand.NEG reg/mem16F7 /3Performs a two’s complement negation on a 16-bitregister or memory operand.NEG reg/mem32F7 /3Performs a two’s complement negation on a 32-bitregister or memory operand.NEG reg/mem64F7 /3Performs a two’s complement negation on a 64-bitregister or memory operand.Related InstructionsAND, NOT, OR, XORrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand is in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPInstruction ReferenceNEG175AMD64 TechnologyException24594—Rev. 3.13—July 2007VirtualReal 8086 ProtectedCause of ExceptionPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.176NEGInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyNOPNo OperationDoes nothing. This one-byte instruction increments the rIP to point to next instruction in theinstruction stream, but does not affect the machine state in any other way.The NOP instruction is an alias for XCHG rAX,rAX.MnemonicNOPOpcode90DescriptionPerforms no operation.Related InstructionsNonerFLAGS AffectedNoneExceptionsNoneInstruction ReferenceNOP177AMD64 Technology24594—Rev. 3.13—July 2007NOTOne’s Complement NegationPerforms the one’s complement negation of the value in the specified register or memory location byinverting each bit of the value.The memory-operand forms of the NOT instruction support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionNOT reg/mem8F6 /2Complements the bits in an 8-bit register or memoryoperand.NOT reg/mem16F7 /2Complements the bits in a 16-bit register or memoryoperand.NOT reg/mem32F7 /2Complements the bits in a 32-bit register or memoryoperand.NOT reg/mem64F7 /2Compliments the bits in a 64-bit register or memoryoperand.Related InstructionsAND, NEG, OR, XORrFLAGS AffectedNoneExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference is performed while alignmentchecking was enabled.178NOTInstruction Reference24594—Rev.
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