Volume 3 General-Purpose and System Instructions (794097), страница 40
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Like the CMOVcc instructions(page 91), the SETcc instructions can replace two instructions—a conditional jump and a move.Replacing conditional jumps with conditional sets can help avoid branch-prediction penalties that mayresult from conditional jumps.If the logical value “true” (logical one) is represented in a high-level language as an integer with all bitsset to 1, software can accomplish such representation by first executing the opposite SETccinstruction—for example, the opposite of SETZ is SETNZ—and then decrementing the result.A ModR/M byte is used to identify the operand. The reg field in the ModR/M byte is unused.MnemonicOpcodeDescriptionSETO reg/mem80F 90 /0Set byte if overflow (OF = 1).SETNO reg/mem80F 91 /0Set byte if not overflow (OF = 0).SETB reg/mem8SETC reg/mem8SETNAE reg/mem80F 92 /0Set byte if below (CF = 1).Set byte if carry (CF = 1).Set byte if not above or equal (CF = 1).SETNB reg/mem8SETNC reg/mem8SETAE reg/mem80F 93 /0Set byte if not below (CF = 0).Set byte if not carry (CF = 0).Set byte if above or equal (CF = 0).SETZ reg/mem8SETE reg/mem80F 94 /0Set byte if zero (ZF = 1).Set byte if equal (ZF = 1).SETNZ reg/mem8SETNE reg/mem80F 95 /0Set byte if not zero (ZF = 0).Set byte if not equal (ZF = 0).SETBE reg/mem8SETNA reg/mem80F 96 /0Set byte if below or equal (CF = 1 or ZF = 1).Set byte if not above (CF = 1 or ZF = 1).SETNBE reg/mem8SETA reg/mem80F 97 /0Set byte if not below or equal (CF = 0 and ZF = 0).Set byte if above (CF = 0 and ZF = 0).SETS reg/mem80F 98 /0Set byte if sign (SF = 1).SETNS reg/mem80F 99 /0Set byte if not sign (SF = 0).SETP reg/mem8SETPE reg/mem80F 9A /0Set byte if parity (PF = 1).Set byte if parity even (PF = 1).SETNP reg/mem8SETPO reg/mem80F 9B /0Set byte if not parity (PF = 0).Set byte if parity odd (PF = 0).Instruction ReferenceSETcc225AMD64 Technology24594—Rev.
3.13—July 2007MnemonicOpcodeDescriptionSETL reg/mem8SETNGE reg/mem80F 9C /0Set byte if less (SF <> OF).Set byte if not greater or equal (SF <> OF).SETNL reg/mem8SETGE reg/mem80F 9D /0Set byte if not less (SF = OF).Set byte if greater or equal (SF = OF).SETLE reg/mem8SETNG reg/mem80F 9E /0Set byte if less or equal (ZF = 1 or SF <> OF).Set byte if not greater (ZF = 1 or SF <> OF).SETNLE reg/mem8SETG reg/mem80F 9F /0Set byte if not less or equal (ZF = 0 and SF = OF).Set byte if greater (ZF = 0 and SF = OF).Related InstructionsNonerFLAGS AffectedNoneExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.XA page fault resulted from the execution of the instruction.General protection,#GPPage fault, #PF226Cause of ExceptionXSETccInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologySFENCEStore FenceActs as a barrier to force strong memory ordering (serialization) between store instructions precedingthe SFENCE and store instructions that follow the SFENCE. Stores to differing memory types, orwithin the WC memory type, may become visible out of program order; the SFENCE instructionen1sures that the system completes all previous stores in such a way that they are globally visiblebefore executing subsequent stores. This includes emptying the store buffer and all write-combiningbuffers.The SFENCE instruction is weakly-ordered with respect to load instructions, data and instructionprefetches, and the LFENCE instruction. Speculative loads initiated by the processor, or specifiedexplicitly using cache-prefetch instructions, can be reordered around an SFENCE.In addition to store instructions, SFENCE is strongly ordered with respect to other SFENCEinstructions, MFENCE instructions, and serializing instructions.
Further details on the use ofMFENCE to order accesses among differing memory types may be found in AMD64 ArchitectureProgrammer’s Manual Volume 2: System Programming, section 7.4 “Memory Types” on page 168.Support for the SFENCE instruction is indicated when the SSE bit (bit 25) is set to 1 in EDX afterexecuting CPUID function 0000_0001h.MnemonicOpcodeSFENCE0F AE F8DescriptionForce strong ordering of (serialized) store operations.Related InstructionsLFENCE, MFENCErFLAGS AffectedNoneExceptionsExceptionInvalid Opcode,#UDVirtualReal 8086 ProtectedXXXCause of ExceptionThe SSE instructions are not supported, as indicated by EDXbit 25 of CPUID function 0000_0001h; and the AMDextensions to MMX are not supported, as indicated by EDX bit22 of CPUID function 8000_0001h.1.Instruction ReferenceSFENCE227AMD64 Technology24594—Rev.
3.13—July 2007SHLShift LeftThis instruction is synonymous with the SAL instruction. For information, see “SAL SHL” onpage 216.228SHLInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologySHLDShift Left DoubleShifts the bits of a register or memory location (first operand) to the left by the number of bit positionsin an unsigned immediate value or the CL register (third operand), and shifts in a bit pattern (secondoperand) from the right. At the end of the shift operation, the CF flag contains the last bit shifted out ofthe first operand.The processor masks the upper three bits of the count operand, thus restricting the count to a numberbetween 0 and 31. When the destination is 64 bits wide, the processor masks the upper two bits of thecount, providing a count in the range of 0 to 63.
If the masked count is greater than the operand size,the result in the destination register is undefined.If the shift count is 0, no flags are modified.If the count is 1 and the sign of the operand being shifted changes, the instruction sets the OF flag to 1.If the count is greater than 1, OF is undefined.MnemonicOpcodeDescriptionSHLD reg/mem16, reg16, imm80F A4 /r ibShift bits of a 16-bit destination register or memoryoperand to the left the number of bits specified in an 8bit immediate value, while shifting in bits from thesecond operand.SHLD reg/mem16, reg16, CL0F A5 /rShift bits of a 16-bit destination register or memoryoperand to the left the number of bits specified in the CLregister, while shifting in bits from the second operand.SHLD reg/mem32, reg32, imm80F A4 /r ibShift bits of a 32-bit destination register or memoryoperand to the left the number of bits specified in an 8bit immediate value, while shifting in bits from thesecond operand.SHLD reg/mem32, reg32, CL0F A5 /rShift bits of a 32-bit destination register or memoryoperand to the left the number of bits specified in the CLregister, while shifting in bits from the second operand.SHLD reg/mem64, reg64, imm80F A4 /r ibShift bits of a 64-bit destination register or memoryoperand to the left the number of bits specified in an 8bit immediate value, while shifting in bits from thesecond operand.SHLD reg/mem64, reg64, CL0F A5 /rShift bits of a 64-bit destination register or memoryoperand to the left the number of bits specified in the CLregister, while shifting in bits from the second operand.Related InstructionsSHRD, SAL, SAR, SHR, SHLInstruction ReferenceSHLD229AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMUMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.230SHLDInstruction Reference24594—Rev.
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