Volume 3 General-Purpose and System Instructions (794097), страница 41
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3.13—July 2007AMD64 TechnologySHRShift RightShifts the bits of a register or memory location (first operand) to the right through the CF bit by thenumber of bit positions in an unsigned immediate value or the CL register (second operand). Theinstruction discards bits shifted out of the CF flag.
At the end of the shift operation, the CF flagcontains the last bit shifted out of the first operand.For each bit shift, the instruction clears the most-significant bit to 0.The effect of this instruction is unsigned division by powers of two.The processor masks the upper three bits of the count operand, thus restricting the count to a numberbetween 0 and 31. When the destination is 64 bits wide, the processor masks the upper two bits of thecount, providing a count in the range of 0 to 63.For 1-bit shifts, the instruction sets the OF flag to the most-significant bit of the original value.
If thecount is greater than 1, the OF flag is undefined.If the shift count is 0, no flags are modified.MnemonicOpcodeDescriptionSHR reg/mem8, 1D0 /5Shift an 8-bit register or memory operand right 1 bit.SHR reg/mem8, CLD2 /5Shift an 8-bit register or memory operand right thenumber of bits specified in the CL register.SHR reg/mem8, imm8C0 /5 ibShift an 8-bit register or memory operand right thenumber of bits specified by an 8-bit immediate value.SHR reg/mem16, 1D1 /5Shift a 16-bit register or memory operand right 1 bit.SHR reg/mem16, CLD3 /5Shift a 16-bit register or memory operand right thenumber of bits specified in the CL register.SHR reg/mem16, imm8C1 /5 ibShift a 16-bit register or memory operand right thenumber of bits specified by an 8-bit immediate value.SHR reg/mem32, 1D1 /5Shift a 32-bit register or memory operand right 1 bit.SHR reg/mem32, CLD3 /5Shift a 32-bit register or memory operand right thenumber of bits specified in the CL register.SHR reg/mem32, imm8C1 /5 ibShift a 32-bit register or memory operand right thenumber of bits specified by an 8-bit immediate value.SHR reg/mem64, 1D1 /5Shift a 64-bit register or memory operand right 1 bit.SHR reg/mem64, CLD3 /5Shift a 64-bit register or memory operand right thenumber of bits specified in the CL register.SHR reg/mem64, imm8C1 /5 ibShift a 64-bit register or memory operand right thenumber of bits specified by an 8-bit immediate value.Instruction ReferenceSHR231AMD64 Technology24594—Rev.
3.13—July 2007Related InstructionsSHL, SAL, SAR, SHLD, SHRDrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMUMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.232SHRInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologySHRDShift Right DoubleShifts the bits of a register or memory location (first operand) to the right by the number of bitpositions in an unsigned immediate value or the CL register (third operand), and shifts in a bit pattern(second operand) from the left. At the end of the shift operation, the CF flag contains the last bit shiftedout of the first operand.The processor masks the upper three bits of the count operand, thus restricting the count to a numberbetween 0 and 31.
When the destination is 64 bits wide, the processor masks the upper two bits of thecount, providing a count in the range of 0 to 63. If the masked count is greater than the operand size,the result in the destination register is undefined.If the shift count is 0, no flags are modified.If the count is 1 and the sign of the value being shifted changes, the instruction sets the OF flag to 1. Ifthe count is greater than 1, the OF flag is undefined.MnemonicSHRD reg/mem16, reg16, imm8SHRD reg/mem16, reg16, CLSHRD reg/mem32, reg32, imm8SHRD reg/mem32, reg32, CLSHRD reg/mem64, reg64, imm8SHRD reg/mem64, reg64, CLOpcodeDescription0F AC /r ibShift bits of a 16-bit destination register or memoryoperand to the right the number of bits specified in an 8bit immediate value, while shifting in bits from thesecond operand.0F AD /rShift bits of a 16-bit destination register or memoryoperand to the right the number of bits specified in theCL register, while shifting in bits from the secondoperand.0F AC /r ibShift bits of a 32-bit destination register or memoryoperand to the right the number of bits specified in an 8bit immediate value, while shifting in bits from thesecond operand.0F AD /rShift bits of a 32-bit destination register or memoryoperand to the right the number of bits specified in theCL register, while shifting in bits from the secondoperand.0F AC /r ibShift bits of a 64-bit destination register or memoryoperand to the right the number of bits specified in an 8bit immediate value, while shifting in bits from thesecond operand.0F AD /rShift bits of a 64-bit destination register or memoryoperand to the right the number of bits specified in theCL register, while shifting in bits from the secondoperand.Related InstructionsSHLD, SHR, SHL, SAR, SALInstruction ReferenceSHRD233AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMUMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.234SHRDInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologySTCSet Carry FlagSets the carry flag (CF) in the rFLAGS register to one.MnemonicOpcodeSTCDescriptionF9Set the carry flag (CF) to one.Related InstructionsCLC, CMCrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF12120191817161413–1211109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsNoneInstruction ReferenceSTC235AMD64 Technology24594—Rev. 3.13—July 2007STDSet Direction FlagSet the direction flag (DF) in the rFLAGS register to 1. If the DF flag is 0, each iteration of a stringinstruction increments the data pointer (index registers rSI or rDI). If the DF flag is 1, the stringinstruction decrements the pointer. Use the CLD instruction before a string instruction to make the datapointer increment.MnemonicOpcodeSTDDescriptionFDSet the direction flag (DF) to one.Related InstructionsCLD, INSx, LODSx, MOVSx, OUTSx, SCASx, STOSx, CMPSxrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF987642012120191817161413–121110Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags areblank. Undefined flags are U.ExceptionsNone236STDInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologySTOSSTOSBSTOSWSTOSDSTOSQStore StringCopies a byte, word, doubleword, or quadword from the AL, AX, EAX, or RAX registers to thememory location pointed to by ES:rDI and increments or decrements the rDI register according to thestate of the DF flag in the rFLAGS register.If the DF flag is 0, the instruction increments the pointer; otherwise, it decrements the pointer. Itincrements or decrements the pointer by 1, 2, 4, or 8, depending on the size of the value being copied.The forms of the STOSx instruction with an explicit operand use the operand only to specify the type(size) of the value being copied.The no-operands forms specify the type (size) of the value being copied with the mnemonic.The STOSx instructions support the REP prefixes.
For details about the REP prefixes, see “RepeatPrefixes” on page 9. The STOSx instructions can also operate inside a LOOPcc instruction.MnemonicOpcodeDescriptionSTOS mem8AAStore the contents of the AL register to ES:rDI, and thenincrement or decrement rDI.STOS mem16ABStore the contents of the AX register to ES:rDI, and thenincrement or decrement rDI.STOS mem32ABStore the contents of the EAX register to ES:rDI, andthen increment or decrement rDI.STOS mem64ABStore the contents of the RAX register to ES:rDI, andthen increment or decrement rDI.STOSBAAStore the contents of the AL register to ES:rDI, and thenincrement or decrement rDI.STOSWABStore the contents of the AX register to ES:rDI, and thenincrement or decrement rDI.STOSDABStore the contents of the EAX register to ES:rDI, andthen increment or decrement rDI.STOSQABStore the contents of the RAX register to ES:rDI, andthen increment or decrement rDI.Related InstructionsLODSx, MOVSxInstruction ReferenceSTOSx237AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedXXGeneral protection,#GPCause of ExceptionXA memory address exceeded the ES segment limit or wasnon-canonical.XThe ES segment was a non-writable segment.XA null ES segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.238STOSxInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologySUBSubtractSubtracts an immediate value or the value in a register or memory location (second operand) from aregister or a memory location (first operand) and stores the result in the first operand location. Animmediate value is sign-extended to the length of the first operand.This instruction evaluates the result for both signed and unsigned data types and sets the OF and CFflags to indicate a borrow in a signed or unsigned result, respectively.
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