Volume 3 General-Purpose and System Instructions (794097), страница 42
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It sets the SF flag to indicate thesign of a signed result.The forms of the SUB instruction that write to memory support the LOCK prefix. For details about theLOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionSUB AL, imm82C ibSubtract an immediate 8-bit value from the AL registerand store the result in AL.SUB AX, imm162D iwSubtract an immediate 16-bit value from the AX registerand store the result in AX.SUB EAX, imm322D idSubtract an immediate 32-bit value from the EAXregister and store the result in EAX.SUB RAX, imm322D idSubtract a sign-extended immediate 32-bit value fromthe RAX register and store the result in RAX.SUB reg/mem8, imm880 /5 ibSubtract an immediate 8-bit value from an 8-bitdestination register or memory location.SUB reg/mem16, imm1681 /5 iwSubtract an immediate 16-bit value from a 16-bitdestination register or memory location.SUB reg/mem32, imm3281 /5 idSubtract an immediate 32-bit value from a 32-bitdestination register or memory location.SUB reg/mem64, imm3281 /5 idSubtract a sign-extended immediate 32-bit value from a64-bit destination register or memory location.SUB reg/mem16, imm883 /5 ibSubtract a sign-extended immediate 8-bit value from a16-bit register or memory location.SUB reg/mem32, imm883 /5 ibSubtract a sign-extended immediate 8-bit value from a32-bit register or memory location.SUB reg/mem64, imm883 /5 ibSubtract a sign-extended immediate 8-bit value from a64-bit register or memory location.SUB reg/mem8, reg828 /rSubtract the contents of an 8-bit register from an 8-bitdestination register or memory location.SUB reg/mem16, reg1629 /rSubtract the contents of a 16-bit register from a 16-bitdestination register or memory location.SUB reg/mem32, reg3229 /rSubtract the contents of a 32-bit register from a 32-bitdestination register or memory location.SUB reg/mem64, reg6429 /rSubtract the contents of a 64-bit register from a 64-bitdestination register or memory location.Instruction ReferenceSUB239AMD64 Technology24594—Rev.
3.13—July 2007MnemonicOpcodeDescriptionSUB reg8, reg/mem82A /rSubtract the contents of an 8-bit register or memoryoperand from an 8-bit destination register.SUB reg16, reg/mem162B /rSubtract the contents of a 16-bit register or memoryoperand from a 16-bit destination register.SUB reg32, reg/mem322B /rSubtract the contents of a 32-bit register or memoryoperand from a 32-bit destination register.SUB reg64, reg/mem642B /rSubtract the contents of a 64-bit register or memoryoperand from a 64-bit destination register.Related InstructionsADC, ADD, SBBrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.240SUBInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyTESTTest BitsPerforms a bit-wise logical AND on the value in a register or memory location (first operand) with animmediate value or the value in a register (second operand) and sets the flags in the rFLAGS registerbased on the result. While the AND instruction changes the contents of the destination and the flagbits, the TEST instruction changes only the flag bits.MnemonicOpcodeDescriptionTEST AL, imm8A8 ibAND an immediate 8-bit value with the contents of theAL register and set rFLAGS to reflect the result.TEST AX, imm16A9 iwAND an immediate 16-bit value with the contents of theAX register and set rFLAGS to reflect the result.TEST EAX, imm32A9 idAND an immediate 32-bit value with the contents of theEAX register and set rFLAGS to reflect the result.TEST RAX, imm32A9 idAND a sign-extended immediate 32-bit value with thecontents of the RAX register and set rFLAGS to reflectthe result.TEST reg/mem8, imm8F6 /0 ibAND an immediate 8-bit value with the contents of an 8bit register or memory operand and set rFLAGS toreflect the result.TEST reg/mem16, imm16F7 /0 iwAND an immediate 16-bit value with the contents of a16-bit register or memory operand and set rFLAGS toreflect the result.TEST reg/mem32, imm32F7 /0 idAND an immediate 32-bit value with the contents of a32-bit register or memory operand and set rFLAGS toreflect the result.TEST reg/mem64, imm32F7 /0 idAND a sign-extended immediate32-bit value with thecontents of a 64-bit register or memory operand and setrFLAGS to reflect the result.TEST reg/mem8, reg884 /rAND the contents of an 8-bit register with the contentsof an 8-bit register or memory operand and set rFLAGSto reflect the result.TEST reg/mem16, reg1685 /rAND the contents of a 16-bit register with the contentsof a 16-bit register or memory operand and set rFLAGSto reflect the result.TEST reg/mem32, reg3285 /rAND the contents of a 32-bit register with the contentsof a 32-bit register or memory operand and set rFLAGSto reflect the result.TEST reg/mem64, reg6485 /rAND the contents of a 64-bit register with the contentsof a 64-bit register or memory operand and set rFLAGSto reflect the result.Related InstructionsAND, CMPInstruction ReferenceTEST241AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTF02120191817161413–12111098SFZFAFPFCFMMUM076420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.242TESTInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyXADDExchange and AddExchanges the contents of a register (second operand) with the contents of a register or memorylocation (first operand), computes the sum of the two values, and stores the result in the first operandlocation.The forms of the XADD instruction that write to memory support the LOCK prefix.
For details aboutthe LOCK prefix, see “Lock Prefix” on page 8.MnemonicOpcodeDescriptionXADD reg/mem8, reg80F C0 /rExchange the contents of an 8-bit register with thecontents of an 8-bit destination register or memoryoperand and load their sum into the destination.XADD reg/mem16, reg160F C1 /rExchange the contents of a 16-bit register with thecontents of a 16-bit destination register or memoryoperand and load their sum into the destination.XADD reg/mem32, reg320F C1 /rExchange the contents of a 32-bit register with thecontents of a 32-bit destination register or memoryoperand and load their sum into the destination.XADD reg/mem64, reg640F C1 /rExchange the contents of a 64-bit register with thecontents of a 64-bit destination register or memoryoperand and load their sum into the destination.Related InstructionsNonerFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFM2120191817161413–12111098SFZFAFPFCFMMMMM76420Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPInstruction ReferenceXADD243AMD64 TechnologyException24594—Rev. 3.13—July 2007VirtualReal 8086 ProtectedCause of ExceptionPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.244XADDInstruction Reference24594—Rev.
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