Volume 3 General-Purpose and System Instructions (794097), страница 46
Текст из файла (страница 46)
3.13—July 2007IF (temp_RIP > CS.limit)EXCEPTION [#GP(0)]CS.sel = temp_CSCS.base = temp_CS SHL 4RFLAGS.v = temp_RFLAGS // VIF,VIP,VM unchangedRIP = temp_RIPEXITIRET_PROTECTED:IF (RFLAGS.NT=1)IF (LEGACY_MODE)TASK_SWITCHELSEEXCEPTION [#GP(0)]// iret does a task-switch to a previous task// using the ’back link’ field in the tss// (LONG_MODE)// task switches aren’t supported in long modePOP.v temp_RIPPOP.v temp_CSPOP.v temp_RFLAGSIF ((temp_RFLAGS.VM=1) && (CPL=0) && (LEGACY_MODE))IRET_FROM_PROTECTED_TO_VIRTUALtemp_CPL = temp_CS.rplIF ((64BIT_MODE) || (temp_CPL!=CPL)){POP.v temp_RSP// in 64-bit mode, iret always pops ss:rspPOP.v temp_SS}CS = READ_DESCRIPTOR (temp_CS, iret_chk)IF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit)){EXCEPTION [#GP(0)]}CPL = temp_CPLIF ((started in 64-bit mode) || (changing CPL))// ss:rsp were popped, so load them into the registers{SS = READ_DESCRIPTOR (temp_SS, ss_chk)RSP.s = temp_RSP}266IRETxInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyIF (changing CPL){FOR (seg = ES, DS, FS, GS)IF ((seg.attr.dpl < CPL) && ((seg.attr.type = ’data’)|| (seg.attr.type = ’non-conforming-code’))){seg = NULL// can’t use lower dpl data segment at higher cpl}}RFLAGS.v = temp_RFLAGS// VIF,VIP,IOPL only changed if (old_CPL=0)// IF only changed if (old_CPL<=old_RFLAGS.IOPL)// VM unchanged// RF clearedRIP = temp_RIPEXITIRET_VIRTUAL:IF ((RFLAGS.IOPL<3) && (CR4.VME=0))EXCEPTION [#GP(0)]POP.v temp_RIPPOP.v temp_CSPOP.v temp_RFLAGSIF (temp_RIP > CS.limit)EXCEPTION [#GP(0)]IF (RFLAGS.IOPL=3){RFLAGS.v = temp_RFLAGS// VIF,VIP,VM,IOPL unchanged// RF clearedCS.sel = temp_CSCS.base = temp_CS SHL 4RIP = temp_RIPEXIT}// now ((IOPL<3) && (CR4.VME=1)ELSIF ((OPERAND_SIZE=16)&& !((temp_RFLAGS.IF=1) && (RFLAGS.VIP=1))&& (temp_RFLAGS.TF=0)){RFLAGS.w = temp_RFLAGS // RFLAGS.VIF=temp_RFLAGS.IF// IF,IOPL unchanged// RF clearedCS.sel = temp_CSCS.base = temp_CS SHL 4Instruction ReferenceIRETx267AMD64 Technology24594—Rev.
3.13—July 2007RIP = temp_RIPEXIT}ELSE // ((RFLAGS.IOPL<3) && (CR4.VME=1) && ((OPERAND_SIZE=32) ||// ((temp_RFLAGS.IF=1) && (RFLAGS.VIP=1)) || (temp_RFLAGS.TF=1)))EXCEPTION [#GP(0)]IRET_FROM_PROTECTED_TO_VIRTUAL:// temp_RIP already popped// temp_CS already popped// temp_RFLAGS already popped, temp_RFLAGS.VM=1POP.dPOP.dPOP.dPOP.dPOP.dPOP.d268temp_RSPtemp_SStemp_EStemp_DStemp_FStemp_GSCS.sel =CS.base =CS.limit=CS.attr =temp_CS// force the segments to have virtual-mode valuestemp_CS SHL 40x0000FFFF16-bit dpl3 codeSS.sel =SS.base =SS.limit=SS.attr =temp_SStemp_SS SHL 40x0000FFFF16-bit dpl3 stackDS.sel =DS.base =DS.limit=DS.attr =temp_DStemp_DS SHL 40x0000FFFF16-bit dpl3 dataES.sel =ES.base =ES.limit=ES.attr =temp_EStemp_ES SHL 40x0000FFFF16-bit dpl3 dataFS.sel =FS.base =FS.limit=FS.attr =temp_FStemp_FS SHL 40x0000FFFF16-bit dpl3 dataGS.sel =GS.base =GS.limit=GS.attr =temp_GStemp_GS SHL 40x0000FFFF16-bit dpl3 dataIRETxInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyRSP.d = temp_RSPRFLAGS.d = temp_RFLAGSCPL = 3RIP = temp_RIP AND 0x0000FFFFEXITRelated InstructionsINT, INTO, INT3rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCFMMMMMMMMMMMMMMMMM2120191817161413–1211109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flagsare blank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedSegment notpresent, #NP(selector)Stack, #SSXXStack, #SS(selector)XGeneral protection,#GPXXThe return code segment was marked not present.XA memory address exceeded the stack segment limit or wasnon-canonical.XThe SS register was loaded with a non-null segment selectorand the segment was marked not present.XThe target offset exceeded the code segment limit or was noncanonical.IOPL was less than 3 and one of the following conditions wastrue:• CR4.VME was 0.• The effective operand size was 32-bit.• Both the original EFLAGS.VIP and the new EFLAGS.IFwere set.• The new EFLAGS.TF was set.XXInstruction ReferenceCause of ExceptionIRETx was executed in long mode while EFLAGS.NT=1.IRETx269AMD64 TechnologyException24594—Rev.
3.13—July 2007VirtualReal 8086 ProtectedGeneral protection,#GP(selector)Cause of ExceptionXThe return code selector was a null selector.XThe return stack selector was a null selector and the returnmode was non-64-bit mode or CPL was 3.XThe return code or stack descriptor exceeded the descriptortable limit.XThe return code or stack selector’s TI bit was set but the LDTselector was a null selector.XThe segment descriptor for the return code was not a codesegment.XThe RPL of the return code segment selector was less thanthe CPL.XThe return code segment was non-conforming and thesegment selector’s DPL was not equal to the RPL of the codesegment’s segment selector.XThe return code segment was conforming and the segmentselector’s DPL was greater than the RPL of the codesegment’s segment selector.XThe segment descriptor for the return stack was not a writabledata segment.XThe stack segment descriptor DPL was not equal to the RPLof the return code segment selector.XThe stack segment selector RPL was not equal to the RPL ofthe return code segment selector.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.270IRETxInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyLARLoad Access Rights ByteLoads the access rights from the segment descriptor specified by a 16-bit source register or memoryoperand into a specified 16-bit, 32-bit, or 64-bit general-purpose register and sets the zero (ZF) flag inthe rFLAGS register if successful. LAR clears the zero flag if the descriptor is invalid for any reason.The LAR instruction checks that:••••the segment selector is not a null selector.the descriptor is within the GDT or LDT limit.the descriptor DPL is greater than or equal to both the CPL and RPL, or the segment is a conforming code segment.the descriptor type is valid for the LAR instruction.
Valid descriptor types are shown in the following table. LDT and TSS descriptors in 64-bit mode, and call-gate descriptors in long mode, areonly valid if bits 12–8 of doubleword +12 are zero, as shown on page 111 of vol. 2 in Figure 4-22.Valid Descriptor TypeDescriptionLegacy ModeLong ModeAllAllAll code and data descriptors1—Available 16-bit TSS22LDT3—Busy 16-bit TSS4—16-bit call gate5—Task gate99Available 32-bit or 64-bit TSSBBBusy 32-bit or 64-bit TSSCC32-bit or 64-bit call gateIf the segment descriptor passes these checks, the attributes are loaded into the destination generalpurpose register.
If it does not, then the zero flag is cleared and the destination register is not modified.When the operand size is 16 bits, access rights include the DPL and Type fields located in bytes 4 and5 of the descriptor table entry. Before loading the access rights into the destination operand, the loworder word is masked with FF00H.When the operand size is 32 or 64 bits, access rights include the DPL and type as well as the descriptortype (S field), segment present (P flag), available to system (AVL flag), default operation size (D/Bflag), and granularity flags located in bytes 4–7 of the descriptor. Before being loaded into thedestination operand, the doubleword is masked with 00FF_FF00H.Instruction ReferenceLAR271AMD64 Technology24594—Rev.
3.13—July 2007In 64-bit mode, for both 32-bit and 64-bit operand sizes, 32-bit register results are zero-extended to 64bits.This instruction can only be executed in protected mode.MnemonicOpcodeDescriptionLAR reg16, reg/mem160F 02 /rReads the GDT/LDT descriptor referenced by the 16-bitsource operand, masks the attributes with FF00h and savesthe result in the 16-bit destination register.LAR reg32, reg/mem160F 02 /rReads the GDT/LDT descriptor referenced by the 16-bitsource operand, masks the attributes with 00FFFF00h andsaves the result in the 32-bit destination register.LAR reg64, reg/mem160F 02 /rReads the GDT/LDT descriptor referenced by the 16-bitsource operand, masks the attributes with 00FFFF00h andsaves the result in the 64-bit destination register.Related InstructionsARPL, LSL, VERR, VERWrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF420M2120191817161413–1211109876Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to one or zero is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXCause of ExceptionThis instruction is only recognized in protected mode.XA memory address exceeded the stack segment limit or wasnon-canonical.XA memory address exceeded the data segment limit or wasnon-canonical.XA null data segment was used to reference memory.XThe extended attribute bits of a system descriptor was notzero in 64-bit mode.Page fault, #PFXA page fault resulted from the execution of the instruction.Alignment check, #ACXAn unaligned memory reference was performed whilealignment checking was enabled.Stack, #SSGeneral protection,#GP272LARInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyLGDTLoad Global Descriptor Table RegisterLoads the pseudo-descriptor specified by the source operand into the global descriptor table register(GDTR).
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