Volume 3 General-Purpose and System Instructions (794097), страница 49
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CR1, CR5, CR6, CR7, andCR9 through CR15 are all reserved and raise an undefined opcode exception (#UD) if referenced.CR8 can be read and written in 64-bit mode, using a REX prefix. CR8 can be read and written inlegacy mode using the MOV (CRn) opcode, using a LOCK prefix instead of a REX prefix to specifythe additional opcode bit. To verify whether the LOCK prefix can be used in this way, check the statusof ECX bit 4 returned by CPUID function 80000001h.CR8 can also be read and modified using the task priority register described in “System-ControlRegisters” in Volume 2.This instruction is always treated as a register-to-register (MOD = 11) instruction, regardless of theencoding of the MOD field in the MODR/M byte.MOV(CRn) is a privileged instruction and must always be executed at CPL = 0.MOV (CRn) is a serializing instruction.MnemonicOpcodeDescriptionMOV CRn, reg320F 22 /rMove the contents of a 32-bit register to CRnMOV CRn, reg640F 22 /rMove the contents of a 64-bit register to CRnMOV reg32, CRn0F 20 /rMove the contents of CRn to a 32-bit register.MOV reg64, CRn0F 20 /rMove the contents of CRn to a 64-bit register.MOV CR8, reg32F0 0F 22/rMove the contents of a 32-bit register to CR8.MOV CR8, reg64F0 0F 22/rMove the contents of a 64-bit register to CR8.MOV reg32, CR8F0 0F 20/rMove the contents of CR8 into a 32-bit register.MOV reg64, CR8F0 0F 20/rMove the contents of CR8 into a 64-bit register.Related InstructionsCLTS, LMSW, SMSWrFLAGS AffectedNone286MOV (CRn)Instruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyExceptionsExceptionInvalid Instruction,#UDGeneral protection,#GPVirtualReal 8086 ProtectedCause of ExceptionXXXAn illegal control register was referenced (CR1, CR5–CR7,CR9–CR15).XXXThe use of the LOCK prefix to read CR8 in legacy mode is notsupported, as indicated by ECX bit 4 as returned by CPUIDfunction 8000_0001h.XXCPL was not 0.XXAn attempt was made to set CR0.PG = 1 and CR0.PE = 0.XXAn attempt was made to set CR0.CD = 0 and CR0.NW = 1.XXReserved bits were set in the page-directory pointers table(used in the legacy extended physical addressing mode) andthe instruction modified CR0, CR3, or CR4.XXAn attempt was made to write 1 to any reserved bit in CR0,CR3, CR4 or CR8.XXAn attempt was made to set CR0.PG while long mode wasenabled (EFER.LME = 1), but paging address extensionswere disabled (CR4.PAE = 0).XAn attempt was made to clear CR4.PAE while long mode wasactive (EFER.LMA = 1).Instruction ReferenceMOV (CRn)287AMD64 Technology24594—Rev.
3.13—July 2007MOV(DRn)Move to/from Debug RegistersMoves the contents of a debug register into a 32-bit or 64-bit general-purpose register or vice versa.In 64-bit mode, the operand size is fixed at 64 bits without the need for a REX prefix. In non-64-bitmode, the operand size is fixed at 32-bits and the upper 32 bits of the destination are forced to 0.DR0 through DR3 are linear breakpoint address registers. DR6 is the debug status register and DR7 isthe debug control register.
DR4 and DR5 are aliased to DR6 and DR7 if CR4.DE = 0, and are reservedif CR4.DE = 1.DR8 through DR15 are reserved and generate an undefined opcode exception if referenced.These instructions are privileged and must be executed at CPL 0.The MOV DRn,reg32 and MOV DRn,reg64 instructions are serializing instructions.The MOV(DR) instruction is always treated as a register-to-register (MOD = 11) instruction,regardless of the encoding of the MOD field in the MODR/M byte.See “Debug and Performance Resources” in Volume 2 for details.MnemonicOpcodeDescriptionMOV reg32, DRn0F 21 /rMove the contents of DRn to a 32-bit register.MOV reg64, DRn0F 21 /rMove the contents of DRn to a 64-bit register.MOV DRn, reg320F 23 /rMove the contents of a 32-bit register to DRn.MOV DRn, reg640F 23 /rMove the contents of a 64-bit register to DRn.Related InstructionsNonerFLAGS AffectedNoneExceptionsExceptionDebug, #DBInvalid opcode, #UD288VirtualReal 8086 ProtectedCause of ExceptionXXA debug register was referenced while the general detect(GD) bit in DR7 was set.XXDR4 or DR5 was referenced while the debug extensions(DE) bit in CR4 was set.XAn illegal debug register (DR8–DR15) was referenced.MOV(DRn)Instruction Reference24594—Rev.
3.13—July 2007ExceptionAMD64 TechnologyVirtualReal 8086 ProtectedGeneral protection,#GPInstruction ReferenceXCause of ExceptionXCPL was not 0.XA 1 was written to any of the upper 32 bits of DR6 or DR7 in64-bit mode.MOV(DRn)289AMD64 Technology24594—Rev. 3.13—July 2007MWAITMonitor WaitUsed in conjunction with the MONITOR instruction to cause a processor to wait until a store occurs toa specific linear address range from another processor. The previously executed MONITORinstruction causes the processor to enter the monitor event pending state. The MWAIT instruction mayenter an implementation dependent power state until the monitor event pending state is exited.
TheMWAIT instruction has the same effect on architectural state as the NOP instruction.Events that cause an exit from the monitor event pending state include:••A store from another processor matches the address range established by the MONITOR instruction.Any unmasked interrupt, including INTR, NMI, SMI, INIT.••RESET.Any far control transfer that occurs between the MONITOR and the MWAIT.EAX specifies optional hints for the MWAIT instruction.
There are currently no hints defined and allbits should be 0. Setting a reserved bit in EAX is ignored by the processor.ECX specifies optional extensions for the MWAIT instruction. The only extension currently defined isECX bit 0, which allows interrupts to wake MWAIT, even when eFLAGS.IF=0. Support for thisextension is indicated by CPUID. Setting any unsupported bit in ECX results in a #GP exception.CPUID function 5 indicates support for extended features of MONITOR/MWAIT in ECX:••ECX[0] indicates support for enumeration of MONITOR/MWAIT extensions.ECX[1] indicates that MWAIT can use ECX bit 0 to allow interrupts to cause an exit from themonitor event pending state even when eFLAGS.IF=0.The MWAIT instruction can be executed at CPL 0 and is allowed at CPL > 0 only if MSRC001_0015h[MonMwaitUserEn] =1. When MSR C001_0015h[MonMwaitUserEn] is 0, MWAITgenerates #UD at CPL > 0.
(See the appropriate version of the BIOS and Kernel Developer's Guide forspecific details on MSR C001_0015h.)Support for the MWAIT instruction is indicated by ECX bit 3 (Monitor) as returned by CPUIDfunction 0000_0001h. Software MUST check the CPUID bit once per program or library initializationbefore using the MWAIT instruction, or inconsistent behavior may result.
Software designed to run atCPL greater than 0 must also check for availability by testing whether executing MWAIT causes a#UD exception.The use of the MWAIT instruction is contingent upon the satisfaction of the following codingrequirements:••MONITOR must precede the MWAIT and occur in the same loop.MWAIT must be conditionally executed only if the awaited store has not already occurred. (Thisprevents a race condition between the MONITOR instruction arming the monitoring hardwareand the store intended to trigger the monitoring hardware.)290MWAITInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyThe following pseudo-code shows typical usage of a MONITOR/MWAIT pair:EAX = Linear_Address_to_Monitor;ECX = 0; // ExtensionsEDX = 0; // Hintswhile (!matching_store_done ){MONITOR EAX, ECX, EDXIF ( !matching_store_done ) {MWAIT EAX, ECX}}MnemonicOpcodeMWAITDescriptionCauses the processor to stop instruction executionand enter an implementation-dependent optimizedstate until occurrence of a class of events.0F 01 C9Related InstructionsMONITORrFLAGS AffectedNoneExceptionsExceptionRealXVirtual8086 ProtectedXXThe MONITOR/MWAIT instructions are not supported,as indicated by ECX bit 3 (Monitor) as returned byCPUID function 0000_0001h.XXCPL was not zero andMSRC001_0015[MonMwaitUserEn] = 0.XXUnsupported extension bits were set in ECXInvalid opcode, #UDGeneral protection,#GPInstruction ReferenceXCause of ExceptionMWAIT291AMD64 Technology24594—Rev.
3.13—July 2007RDMSRRead Model-Specific RegisterLoads the contents of a 64-bit model-specific register (MSR) specified in the ECX register intoregisters EDX:EAX. The EDX register receives the high-order 32 bits and the EAX register receivesthe low order bits. The RDMSR instruction ignores operand size; ECX always holds the MSR number,and EDX:EAX holds the data. If a model-specific register has fewer than 64 bits, the unimplementedbit positions loaded into the destination registers are undefined.This instruction must be executed at a privilege level of 0 or a general protection exception (#GP) willbe raised.
This exception is also generated if a reserved or unimplemented model-specific register isspecified in ECX.Use the CPUID instruction to determine if this instruction is supported.For more information about model-specific registers, see the documentation for various hardwareimplementations and Volume 2: System Programming.MnemonicOpcodeRDMSR0F 32DescriptionCopy MSR specified by ECX into EDX:EAX.Related InstructionsWRMSR, RDTSC, RDPMCrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDGeneral protection,#GP292VirtualReal 8086 ProtectedXXCause of ExceptionXXThe RDMSR instruction is not supported, as indicated byEDX bit 5 returned by CPUID function 0000_0001h or function8000_0001h.XXCPL was not 0.XThe value in ECX specifies a reserved or unimplementedMSR address.RDMSRInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyRDPMCRead Performance-Monitoring CounterLoads the contents of a 64-bit performance counter register (PerfCtrn) specified in the ECX registerinto registers EDX:EAX. The EDX register receives the high-order 32 bits and the EAX registerreceives the low order 32 bits. The RDPMC instruction ignores operand size; ECX always holds thenumber of the PerfCtr, and EDX:EAX holds the data.The AMD64 architecture currently supports four performance counters: PerfCtr0 through PerfCtr3.
Tospecify the performance counter number in ECX, specify the counter number(0000_0000h–0000_0003h), rather than the performance counter MSR address(C001_0004h–C001_0007h).Programs running at any privilege level can read performance monitor counters if the PCE flag in CR4is set to 1; otherwise this instruction must be executed at a privilege level of 0.This instruction is not serializing. Therefore, there is no guarantee that all instructions have completedat the time the performance counter is read.For more information about performance-counter registers, see the documentation for varioushardware implementations and “Performance Counters” in Volume 2.MnemonicOpcodeRDPMC0F 33DescriptionCopy the performance monitor counter specifiedby ECX into EDX:EAX.Related InstructionsRDMSR, WRMSRrFLAGS AffectedNoneExceptionsExceptionGeneral Protection,#GPVirtualReal 8086 ProtectedXInstruction ReferenceCause of ExceptionXXThe value in ECX specified an unimplemented performancecounter number.XXCPL was not 0 and CR4.PCE = 0.RDPMC293AMD64 Technology24594—Rev.
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