Volume 3 General-Purpose and System Instructions (794097), страница 51
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The SLB must be structured asdescribed in “Secure Loader Block” on page 412 of the AMD64 Architecture Programmer’s ManualVolume 2: System Programming, order# 24593, and is assumed to contain the code for a Secure Loader(SL).This is a Secure Virtual Machine instruction. This instruction generates a #UD exception if SVM isnot enabled. See “Enabling SVM” on page 367 in AMD64 Architecture Programmer’s ManualVolume 2: System Instructions, order# 24593.MnemonicSKINIT EAXOpcodeDescription0F 01 DESecure initialization and jump, with attestation.ActionIF ((EFER.SVMEN == 0) && !(CPUID 8000_0001.ECX[SKINIT]) || (!PROTECTED_MODE))EXCEPTION [#UD]IF (CPL != 0)EXCEPTION [#GP]// This instruction can only be executed// in protected mode with SVM enabled.// This instruction is only allowed at CPL 0.Initialize processor state as for an INIT signalCR0.PE = 1CS.sel = 0x0008CS.attr = 32-bit code, read/executeCS.base = 0CS.limit = 0xFFFFFFFFSS.sel = 0x0010SS.attr = 32-bit stack, read/write, expand upSS.base = 0SS.limit = 0xFFFFFFFFEAX =EDX =ESP =ClearEAX & 0xFFFF0000 // Form SLB base address.family/model/steppingEAX + 0x00010000 // Initial SL stack.GPRs other than EAX, EDX, ESPEFER = 0VM_CR.DPD = 1VM_CR.R_INIT = 1VM_CR.DIS_A20M = 1Enable SL_DEV, to protect 64Kbyte of physical memory starting atInstruction ReferenceSKINIT301AMD64 Technology24594—Rev.
3.13—July 2007the physical address in EAXGIF = 0Read the SL length from offset 0x0002 in the SLBCopy the SL image to the TPM for attestationRead the SL entrypoint offset from offset 0x0000 in the SLBJump to the SL entrypoint, at EIP = EAX+entrypoint offsetRelated InstructionsNone.rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF000000000000000002120191817161413–1211109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedXInvalid opcode, #UDXGeneral protection,#GP302XCause of ExceptionSecure Virtual Machine was not enabled (EFER.SVME=0)and both of the following conditions were true:• SVM-Lock is not available, as indicated by EDX bit 2returned by CPUID function 8000_000Ah.• DEV is not available, as indicated by ECX bit 12 returnedby CPUID function 8000_0001h.Instruction is only recognized in protected mode.XCPL was not zero.SKINITInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologySLDTStore Local Descriptor Table RegisterStores the local descriptor table (LDT) selector to a register or memory destination operand.If the destination is a register, the selector is zero-extended into a 16-, 32-, or 64-bit general purposeregister, depending on operand size.If the destination operand is a memory location, the segment selector is written to memory as a 16-bitvalue, regardless of operand size.This SLDT instruction can only be used in protected mode, but it can be executed at any privilegelevel.MnemonicOpcodeDescriptionSLDT reg160F 00 /0Store the segment selector from the localdescriptor table register to a 16-bit register.SLDT reg320F 00 /0Store the segment selector from the localdescriptor table register to a 32-bit register.SLDT reg640F 00 /0Store the segment selector from the localdescriptor table register to a 64-bit register.SLDT mem160F 00 /0Store the segment selector from the localdescriptor table register to a 16-bit memorylocation.Related InstructionsSIDT, SGDT, STR, LIDT, LGDT, LLDT, LTRrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXCause of ExceptionThis instruction is only recognized in protected mode.XA memory address exceeded the stack segment limit or wasnon-canonical.XA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.Page fault, #PFXA page fault resulted from the execution of the instruction.Alignment check,#ACXAn unaligned memory reference was performed whilealignment checking was enabled.Stack, #SSGeneral protection,#GPInstruction ReferenceSLDT303AMD64 Technology24594—Rev.
3.13—July 2007SMSWStore Machine Status WordStores the lower bits of the machine status word (CR0). The target can be a 16-, 32-, or 64-bit registeror a 16-bit memory operand.This instruction is provided for compatibility with early processors.This instruction can be used at any privilege level (CPL).MnemonicOpcodeDescriptionSMSW reg160F 01 /4Store the low 16 bits of CR0 to a 16-bit register.SMSW reg320F 01 /4Store the low 32 bits of CR0 to a 32-bit register.SMSW reg640F 01 /4Store the entire 64-bit CR0 to a 64-bit register.SMSW mem160F 01 /4Store the low 16 bits of CR0 to memory.Related InstructionsLMSW, MOV(CRn)rFLAGS AffectedNoneExceptionsExceptionStack, #SSVirtualReal 8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.304SMSWInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologySTISet Interrupt FlagSets the interrupt flag (IF) in the rFLAGS register to 1, thereby allowing external interrupts received onthe INTR input. Interrupts received on the non-maskable interrupt (NMI) input are not affected by thisinstruction.In real mode, this instruction sets IF to 1.In protected mode and virtual-8086-mode, this instruction is IOPL-sensitive. If the CPL is less than orequal to the rFLAGS.IOPL field, the instruction sets IF to 1.In protected mode, if IOPL < 3, CPL = 3, and protected mode virtual interrupts are enabled(CR4.PVI = 1), then the instruction instead sets rFLAGS.VIF to 1.
If none of these conditions apply,the processor raises a general protection exception (#GP). For more information, see “Protected ModeVirtual Interrupts” in Volume 2.In virtual-8086 mode, if IOPL < 3 and the virtual-8086-mode extensions are enabled (CR4.VME = 1),the STI instruction instead sets the virtual interrupt flag (rFLAGS.VIF) to 1.If STI sets the IF flag and IF was initially clear, then interrupts are not enabled until after theinstruction following STI.
Thus, if IF is 0, this code will not allow an INTR to happen:STICLIIn the following sequence, INTR will be allowed to happen only after the NOP.STINOPCLIIf STI sets the VIF flag and VIP is already set, a #GP fault will be generated.See “Virtual-8086 Mode Extensions” in Volume 2 for more information about IOPL-sensitiveinstructions.MnemonicSTIOpcodeDescriptionFBSet interrupt flag (IF) to 1.ActionIF (CPL <= IOPL)RFLAGS.IF = 1ELSIF (((VIRTUAL_MODE) && (CR4.VME = 1))|| ((PROTECTED_MODE) && (CR4.PVI = 1) && (CPL = 3))){IF (RFLAGS.VIP = 1)EXCEPTION[#GP(0)]RFLAGS.VIF = 1Instruction ReferenceSTI305AMD64 Technology24594—Rev. 3.13—July 2007}ELSEEXCEPTION[#GP(0)]Related InstructionsCLIrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFM212019IFTFSFZFAFPFCF876420M1817161413–1211109Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
M (modified) is either set to one or cleared to zero. Unaffected flagsare blank. Undefined flags are U.ExceptionsExceptionVirtualReal 8086 ProtectedThe CPL was greater than the IOPL and virtual-modeextensions were not enabled (CR4.VME = 0).XGeneral protection,#GPX306Cause of ExceptionXThe CPL was greater than the IOPL and either the CPL wasnot 3 or protected-mode virtual interrupts were not enabled(CR4.PVI = 0).XThis instruction would set RFLAGS.VIF to 1 andRFLAGS.VIP was already 1.STIInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologySTGISet Global Interrupt FlagSets the global interrupt flag (GIF) to 1. While GIF is zero, all external interrupts are disabled.This is a Secure Virtual Machine instruction. This instruction generates a #UD exception if SVM isnot enabled and ECX.SKINIT as returned by CPUID function 8000_0001 is cleared to 0. See“Enabling SVM” on page 367 in AMD64 Architecture Programmer’s Manual Volume-2: SystemInstructions, order# 24593.MnemonicOpcodeSTGIDescription0F 01 DCSets the global interrupt flag (GIF).Related InstructionsCLGIrFLAGS AffectedNone.ExceptionsExceptionVirtualReal 8086 ProtectedXInvalid opcode, #UDXGeneral protection,#GPInstruction ReferenceXCause of ExceptionSecure Virtual Machine was not enabled (EFER.SVME=0)and both of the following conditions were true:• SVM-Lock is not available, as indicated by EDX bit 2returned by CPUID function 8000_000Ah.• DEV is not available, as indicated by ECX bit 12 returnedby CPUID function 8000_0001h.Instruction is only recognized in protected mode.XCPL was not zero.STGI307AMD64 Technology24594—Rev.
3.13—July 2007STRStore Task RegisterStores the task register (TR) selector to a register or memory destination operand.If the destination is a register, the selector is zero-extended into a 16-, 32-, or 64-bit general purposeregister, depending on the operand size.If the destination is a memory location, the segment selector is written to memory as a 16-bit value,regardless of operand size.The STR instruction can only be used in protected mode, but it can be used at any privilege level.MnemonicOpcodeDescriptionSTR reg160F 00 /1Store the segment selector from the task register to a 16-bitgeneral-purpose register.STR reg320F 00 /1Store the segment selector from the task register to a 32-bitgeneral-purpose register.STR reg640F 00 /1Store the segment selector from the task register to a 64-bitgeneral-purpose register.STR mem160F 00 /1Store the segment selector from the task register to a 16-bitmemory location.Related InstructionsLGDT, LIDT, LLDT, LTR, SIDT, SGDT, SLDTrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXCause of ExceptionThis instruction is only recognized in protected mode.XA memory address exceeded the stack segment limit or wasnon-canonical.XA memory address exceeded a data segment limit or wasnon-canonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.Page fault, #PFXA page fault resulted from the execution of the instruction.Alignment check, #ACXAn unaligned memory reference was performed whilealignment checking was enabled.Stack, #SSGeneral protection,#GP308STRInstruction Reference24594—Rev.
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