Volume 3 General-Purpose and System Instructions (794097), страница 48
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Valid descriptor types are shown in the following table. LDT and TSS descriptors in 64-bit mode are only valid if bits 12–8 of doubleword+12 are zero, as shown on Figure 4-22 on page 89 of Volume 2: System Programming.•Valid Descriptor TypeDescriptionLegacy ModeLong Mode——All code and data descriptors1—Available 16-bit TSS22LDT3—Busy 16-bit TSS99Available 32-bit or 64-bit TSSBBBusy 32-bit or 64-bit TSSIf the segment selector passes these checks and the segment limit is loaded into the destination generalpurpose register, the instruction sets the zero flag of the rFLAGS register to 1. If the selector does notpass the checks, then LSL clears the zero flag to 0 and does not modify the destination.The instruction calculates the segment limit to 32 bits, taking the 20-bit limit and the granularity bitinto account. When the operand size is 16 bits, it truncates the upper 16 bits of the 32-bit adjustedsegment limit and loads the lower 16-bits into the target register.MnemonicLSL reg16, reg/mem16280Opcode0F 03 /rDescriptionLoads a 16-bit general-purpose register with the segmentlimit for a selector specified in a 16-bit memory or registeroperand.LSLInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyLSL reg32, reg/mem160F 03 /rLoads a 32-bit general-purpose register with the segmentlimit for a selector specified in a 16-bit memory or registeroperand.LSL reg64, reg/mem160F 03 /rLoads a 64-bit general-purpose register with the segmentlimit for a selector specified in a 16-bit memory or registeroperand.Related InstructionsARPL, LAR, VERR, VERWrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF420M2120191817161413–1211109876Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXCause of ExceptionThis instruction is only recognized in protected mode.XA memory address exceeded the stack segment limit or wasnon-canonical.XA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.XThe extended attribute bits of a system descriptor was notzero in 64-bit mode.Page fault, #PFXA page fault resulted from the execution of the instruction.Alignment check,#ACXAn unaligned memory reference was performed whilealignment checking was enabled.Stack, #SSGeneral protection,#GPInstruction ReferenceLSL281AMD64 Technology24594—Rev.
3.13—July 2007LTRLoad Task RegisterLoads the specified segment selector into the visible portion of the task register (TR). The processoruses the selector to locate the descriptor for the TSS in the global descriptor table. It then loads thisdescriptor into the hidden portion of TR. The TSS descriptor in the GDT is marked busy, but no taskswitch is made.If the source operand is null, a general protection exception (#GP) is generated.In legacy and compatibility modes, the TSS descriptor is 8 bytes long and contains a 32-bit baseaddress.In 64-bit mode, the instruction references a 64-bit descriptor to load a 64-bit base address.
The TSStype (09H) is redefined in 64-bit mode for use as the 16-byte TSS descriptor.This instruction must be executed in protected mode when the current privilege level is 0. It is onlyprovided for use by operating system software.The operand size attribute has no effect on this instruction.LTR is a serializing instruction.MnemonicOpcodeLTR reg/mem16DescriptionLoad the 16-bit segment selector into the task register andload the TSS descriptor from the GDT.0F 00 /3Related InstructionsLGDT, LIDT, LLDT, STR, SGDT, SIDT, SLDTrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXCause of ExceptionThis instruction is only recognized in protected mode.Segment not present,#NP (selector)XThe TSS descriptor was marked not present.Stack, #SSXA memory address exceeded the stack segment limit or wasnon-canonical.282LTRInstruction Reference24594—Rev.
3.13—July 2007ExceptionAMD64 TechnologyVirtualReal 8086 ProtectedGeneral protection,#GPGeneral protection,#GP(selector)Page fault, #PFInstruction ReferenceCause of ExceptionXA memory address exceeded a data segment limit or wasnon-canonical.XCPL was not 0.XA null data segment was used to reference memory.XThe new TSS selector was a null selector.XThe source selector did not point into the GDT.XThe descriptor was beyond the GDT limit.XThe descriptor was not an available TSS descriptor.XThe descriptor's extended attribute bits were not zero in 64bit mode.XThe new TSS base address was non-canonical.XA page fault resulted from the execution of the instruction.LTR283AMD64 Technology24594—Rev.
3.13—July 2007MONITORSetup Monitor AddressEstablishes a linear address range of memory for hardware to monitor and puts the processor in themonitor event pending state. When in the monitor event pending state, the monitoring hardwaredetects stores to the specified linear address range and causes the processor to exit the monitor eventpending state. The MWAIT instruction uses the state of the monitor hardware.The address range should be a write-back memory type. Executing MONITOR on an address range fora non-write-back memory type is not guaranteed to cause the processor to enter the monitor eventpending state.
The size of the linear address range that is established by the MONITOR instruction canbe determined by CPUID function 0000_0005h.The [rAX] register provides the effective address. The DS segment is the default segment used tocreate the linear address. Segment overrides may be used with the MONITOR instruction.The ECX register specifies optional extensions for the MONITOR instruction.
There are currently noextensions defined and setting any bits in ECX will result in a #GP exception. The ECX registeroperand is implicitly 32-bits.The EDX register specifies optional hints for the MONITOR instruction. There are currently no hintsdefined and EDX is ignored by the processor. The EDX register operand is implicitly 32-bits.The MONITOR instruction can be executed at CPL 0 and is allowed at CPL > 0only if MSR C001_0015h[MonMwaitUserEn] = 1. When MSR C001_0015h[MonMwaitUserEn] = 0,MONITOR generates #UD at CPL > 0.
(See the appropriate version of the BIOS and KernelDeveloper's Guide for specific details on MSR C001_0015h.)MONITOR performs the same segmentation and paging checks as a 1-byte read.Support for the MONITOR instruction is indicated by ECX bit 3 (Monitor) as returned by CPUIDfunction 0000_0001h. Software must check the CPUID bit once per program or library initializationbefore using the MONITOR instruction, or inconsistent behavior may result. Software designed to runat CPL greater than 0 must also check for availability by testing whether executing MONITOR causesa #UD exception.The following pseudo-code shows typical usage of a MONITOR/MWAIT pair:EAX = Linear_Address_to_Monitor;ECX = 0; // ExtensionsEDX = 0; // Hintswhile (!matching_store_done){MONITOR EAX, ECX, EDXIF (!matching_store_done) {MWAIT EAX, ECX}}284MONITORInstruction Reference24594—Rev.
3.13—July 2007MnemonicAMD64 TechnologyOpcodeMONITORDescriptionEstablishes a linear address range to be monitoredby hardware and activates the monitor hardware.0F 01 C8Related InstructionsMWAITrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedXXThe MONITOR/MWAIT instructions are notsupported, as indicated by ECX bit 3 (Monitor) asreturned by CPUID function 0000_0001h.XXCPL was not zero andMSR C001_0015[MonMwaitUserEn] = 0.XXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XXXECX was non-zero.XA null data segment was used to reference memory.XA page fault resulted from the execution of theinstruction.XInvalid opcode, #UDStack, #SSGeneral protection, #GPPage Fault, #PFInstruction ReferenceCause of ExceptionXMONITOR285AMD64 Technology24594—Rev.
3.13—July 2007MOV (CRn)Move to/from Control RegistersMoves the contents of a 32-bit or 64-bit general-purpose register to a control register or vice versa.In 64-bit mode, the operand size is fixed at 64 bits without the need for a REX prefix. In non-64-bitmode, the operand size is fixed at 32 bits and the upper 32 bits of the destination are forced to 0.CR0 maintains the state of various control bits. CR2 and CR3 are used for page translation. CR4 holdsvarious feature enable bits. CR8 is used to prioritize external interrupts.
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