Volume 3 General-Purpose and System Instructions (794097), страница 58
Текст из файла (страница 58)
3.13—July 2007AMD64 TechnologyTable A-6. One-Byte and Two-Byte Opcode ModRM Extensions (continued)GroupNumberPrefix Opcode66Group 17Group PNote:1.2.3.4.none,F2, F3n/a.0F 780F 0DModRM reg Field/3/4/0/1/2/5/6/7EXTRQinvalidinvalidinvalidinvalidinvalidinvalidinvalidinvalidinvalidinvalidinvalidinvalidinvalidinvalidVdq, Ib, IbinvalidPREFETCH PREFETCHExclusiveModifiedPrefetch PREFETCH PrefetchReserved4ModifiedReserved4PrefetchReserved4Prefetch4ReservedPrefetchReserved4See Table A-7 on page 351 for ModRM extensions of this two-byte opcode.Invalid in 64-bit mode.This instruction takes a ModRM byte.Reserved prefetch encodings are aliased to the /0 encoding (PREFETCH Exclusive) for future compatibility.A.2.5 ModRM Extensions to Opcodes 0F 01 and 0F AETable A-7 shows the ModRM r/m field encodings for the 0F 01 and 0F AE opcodes, shown inTable A-6.
The 0F 01 opcode is shared by several system instructions, and the 0F AE opcode is sharedby several media and fence instructions. The opcodes are differentiated by the fact that the binary valueof the ModRM mod field is always 11 for these instructions. The ModRM mod field can be any valueexcept 11 for the instructions having an explicit memory operand.Table A-7. Opcode 0F 01 and 0F AE ModRM ExtensionsOpcode0F 01 /7mod=110F 01 /3mod=110F 01 /1mod=110F AE /5mod=110F AE /6mod=110F AE /7mod=11010F 01 F8SWAPGS0F 01 D8VMRUN0F 01 C8MONITOR0F 01 F9RDTSCP0F 01 D9VMMCALL0F 01 C9MWAIT2ModRM r/m Field34567invalidinvalidinvalidinvalidinvalidinvalid0F 01 DAVMLOAD0F 01 DBVMSAVE0F 01 DCSTGI0F 01 DDCLGI0F 01 DESKINIT0F 01 DFINVLPGAinvalidinvalidinvalidinvalidinvalidinvalidLFENCEMFENCESFENCEA.2.6 3DNow!™ OpcodesThe 64-bit media instructions include the MMX™ instructions and the AMD 3DNow!™ instructions.The MMX instructions are encoded using two opcode bytes, as described in “Two-Byte Opcodes” onpage 342.The 3DNow! instructions are encoded using two 0Fh opcode bytes and an immediate byte that islocated at the last byte position of the instruction encoding.
Thus, the format for 3DNow! instructionsis:Opcode and Operand Encodings351AMD64 Technology24594—Rev. 3.13—July 20070Fh 0Fh [ModRM] [SIB] [displacement] imm8_opcodeTable A-8 on page 352 and Table A-9 on page 353 show the immediate byte following the opcodebytes for 3DNow! instructions. In these tables, rows show the high nibble of the immediate byte, andcolumns show the low nibble of the immediate byte. Table A-8 shows the immediate bytes whose lownibble is in the range 0–7h. Table A-9 shows the same for immediate bytes whose low nibble is in therange 8–Fh.Byte values shown as reserved in these tables have implementation-specific functions, which caninclude an invalid-opcode exception.Table A-8. Immediate Byte for 3DNow!™ Opcodes, Low Nibble 0–7hNibble10123456789ABCDEF01234567reservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedPFCMPGEreservedreservedreservedPFMINreservedPFRCPPFRSQRTPq, QqPq, QqPFCMPGTPq, QqPq, QqreservedPFRCPIT1PFRSQIT1Pq, QqPq, QqreservedPFRCPIT2PMULHRWreservedreservedreservedPFMAXreservedreservedreservedPFMULPq, QqPq, QqreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedPq, QqPq, QqPFCMPEQPq, QqPq, QqNote:1.
All 3DNow!™ opcodes consist of two 0Fh bytes. This table shows the immediate byte for 3DNow! opcodes. Rowsshow the high nibble of the immediate byte. Columns show the low nibble of the immediate byte.352Opcode and Operand Encodings24594—Rev. 3.13—July 2007AMD64 TechnologyTable A-9. Immediate Byte for 3DNow!™ Opcodes, Low Nibble 8–FhNibble10123456789ABCDEF89ABCDEFreservedreservedreservedreservedPI2FWPq, QqPI2FDPq, QqreservedreservedreservedreservedreservedreservedreservedreservedPF2IWPF2IDPq, QqPq, QqreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedPFNACCreservedreservedreservedPFPNACCreservedPq, QqreservedreservedPFSUBPq, QqreservedreservedreservedPq, QqreservedreservedPFSUBRreservedreservedreservedPq, QqreservedreservedreservedPq, QqreservedPFADDPFACCreservedPq, QqPSWAPDreservedreservedreservedPAVGUSBPq, QqPq, QqreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedreservedNote:1.
All 3DNow!™ opcodes consist of two 0Fh bytes. This table shows the immediate byte for 3DNow! opcodes. Rowsshow the high nibble of the immediate byte. Columns show the low nibble of the immediate byte.A.2.7 x87 EncodingsAll x87 instructions begin with an opcode byte in the range D8h to DFh, as shown in Table A-2 onpage 342. These opcodes are followed by a ModRM byte that further defines the opcode. Table A-10shows both the opcode byte and the ModRM byte for each x87 instruction.There are two significant ranges for the ModRM byte for x87 opcodes: 00–BFh and C0–FFh. Whenthe value of the ModRM byte falls within the first range, 00–BFh, the opcode uses only the reg field tofurther define the opcode. When the value of the ModRM byte falls within the second range, C0–FFh,the opcode uses the entire ModRM byte to further define the opcode.Opcode and Operand Encodings353AMD64 Technology24594—Rev. 3.13—July 2007Byte values shown as reserved or invalid in Table A-10 have implementation-specific functions, whichcan include an invalid-opcode exception.The basic instructions FNSTENV, FNSTCW, FNCLEX, FNINIT, FNSAVE, FNSTSW, and FNSTSWdo not check for possible floating point exceptions before operating.
Utility versions of thesemnemonics are provided that insert an FWAIT (opcode 9B) before the corresponding non-waitinginstruction. These are FSTENV, FSTCW, FCLEX, FINIT, FSAVE, and FSTSW. For furtherinformation on wait and non-waiting versions of these instructions, see their corresponding pages inVolume 5.354Opcode and Operand Encodings24594—Rev. 3.13—July 2007AMD64 TechnologyTable A-10. x87 Opcodes and ModRM ExtensionsOpcodeModRMmodFieldModRM reg Field/0/1/2/3!11FADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRmem32realmem32realmem32realmem32realmem32realmem32real/4/5/6/700–BFmem32real mem32realC0C8D0D8E0E8F0F8FADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRST(0),ST(0)ST(0), ST(0) ST(0), ST(0)C9D1D9E1E9F1F9FADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRST(0), ST(1) ST(0), ST(1) ST(0), ST(1) ST(0), ST(1)ST(0),ST(1)ST(0), ST(1) ST(0), ST(1)C2CAD2DAE2EAF2FAFADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRST(0),ST(2)11ST(0),ST(0)C1ST(0),ST(1)D8ST(0), ST(0) ST(0), ST(0) ST(0), ST(0) ST(0), ST(0)ST(0), ST(2) ST(0), ST(2) ST(0), ST(2) ST(0), ST(2)ST(0),ST(2)ST(0), ST(2) ST(0), ST(2)C3CBD3DBE3EBF3FBFADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRST(0),ST(3)ST(0), ST(3) ST(0), ST(3) ST(0), ST(3) ST(0), ST(3)ST(0),ST(3)ST(0), ST(3) ST(0), ST(3)C4CCD4DCE4ECF4FCFADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRST(0),ST(4)ST(0), ST(4) ST(0), ST(4) ST(0), ST(4) ST(0), ST(4)ST(0),ST(4)ST(0), ST(4) ST(0), ST(4)C5CDD5DDE5EDF5FDFADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRST(0),ST(5)ST(0), ST(5) ST(0), ST(5) ST(0), ST(5) ST(0), ST(5)ST(0),ST(5)ST(0), ST(5) ST(0), ST(5)C6CED6DEE6EEF6FEFADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRST(0),ST(6)ST(0), ST(6) ST(0), ST(6) ST(0), ST(6) ST(0), ST(6)ST(0),ST(6)ST(0), ST(6) ST(0), ST(6)C7CFD7DFE7EFF7FFFADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRST(0),ST(7)ST(0), ST(7) ST(0), ST(7) ST(0), ST(7) ST(0), ST(7)Opcode and Operand EncodingsST(0),ST(7)ST(0), ST(7) ST(0), ST(7)355AMD64 Technology24594—Rev.
3.13—July 2007Table A-10. x87 Opcodes and ModRM Extensions (continued)OpcodeModRMmodFieldModRM reg Field/0/1/2/3FLDinvalidFSTFSTP/4/5/6/7FLDENVFLDCWFNSTENVFNSTCWmem1600–BF!11mem16mem14/28envC0C8mem32realD0D8E0E8F0F8FLDFXCHFNOPreservedFCHSFLD1F2XM1FPREMST(0),ST(0)ST(0), ST(0)mem32realD911356mem32real mem14/28envC1C9D1D9E1E9F1F9FLDFXCHinvalidreservedFABSFLDL2TFYL2XFYL2XP1ST(0),ST(1)ST(0), ST(1)C2CAD2DAE2EAF2FAFLDFXCHinvalidreservedinvalidFLDL2EFPTANFSQRTST(0),ST(2)ST(0), ST(2)C3CBD3DBE3EBF3FBFLDFXCHinvalidreservedinvalidFLDPIFPATANFSINCOSST(0),ST(3)ST(0), ST(3)C4CCD4DCE4ECF4FCFLDFXCHinvalidreservedFTSTFLDLG2FXTRACTFRNDINTST(0),ST(4)ST(0), ST(4)C5CDD5DDE5EDF5FDFLDFXCHinvalidreservedFXAMFLDLN2FPREM1FSCALEST(0),ST(5)ST(0), ST(5)C6CED6DEE6EEF6FEFLDFXCHinvalidreservedinvalidFLDZFDECSTPFSINST(0),ST(6)ST(0), ST(6)C7CFD7DFE7EFF7FFFLDFXCHinvalidreservedinvalidinvalidFINCSTPFCOSST(0),ST(7)ST(0), ST(7)Opcode and Operand Encodings24594—Rev.
3.13—July 2007AMD64 TechnologyTable A-10. x87 Opcodes and ModRM Extensions (continued)OpcodeModRMmodFieldModRM reg Field/0/1/2/3/4/5/6/7FIADDFIMULFICOMFICOMPFISUBFISUBRFIDIVFIDIVRmem32intmem32intC0C8mem32intmem32intmem32intmem32intmem32intmem32intD0D8E0E8F0FCMOVBFCMOVEF8FCMOVBEFCMOVUinvalidinvalidinvalidinvalid00–BF!11ST(0),ST(0)C1C9D1D9E1E9F1F9FCMOVBFCMOVEFCMOVBEFCMOVUinvalidFUCOMPPinvalidinvalidST(0),ST(1)11ST(0), ST(1) ST(0), ST(1) ST(0), ST(1)C2CAD2DAE2EAF2FAFCMOVBFCMOVEFCMOVBEFCMOVUinvalidinvalidinvalidinvalidST(0),ST(2)DAST(0), ST(0) ST(0), ST(0) ST(0), ST(0)ST(0), ST(2) ST(0), ST(2) ST(0), ST(2)C3CBD3DBE3EBF3FBFCMOVBFCMOVEFCMOVBEFCMOVUinvalidinvalidinvalidinvalidST(0),ST(3)ST(0), ST(3) ST(0), ST(3) ST(0), ST(3)C4CCD4DCE4ECF4FCFCMOVBFCMOVEFCMOVBEFCMOVUinvalidinvalidinvalidinvalidST(0),ST(4)ST(0), ST(4) ST(0), ST(4) ST(0), ST(4)C5CDD5DDE5EDF5FDFCMOVBFCMOVEFCMOVBEFCMOVUinvalidinvalidinvalidinvalidST(0),ST(5)ST(0), ST(5) ST(0), ST(5) ST(0), ST(5)C6CED6DEE6EEF6FEFCMOVBFCMOVEFCMOVBEFCMOVUinvalidinvalidinvalidinvalidST(0),ST(6)ST(0), ST(6) ST(0), ST(6) ST(0), ST(6)C7CFD7DFE7EFF7FFFCMOVBFCMOVEFCMOVBEFCMOVUinvalidinvalidinvalidinvalidST(0),ST(7)ST(0), ST(7) ST(0), ST(7) ST(0), ST(7)Opcode and Operand Encodings357AMD64 Technology24594—Rev.
3.13—July 2007Table A-10. x87 Opcodes and ModRM Extensions (continued)OpcodeModRMmodFieldModRM reg Field/0/1/2/3/4/5/6FLDinvalid/700–BF!11FILDFISTTPFISTFISTPmem32intmem32intmem32intmem32intC0C8D0D8FCMOVNB FCMOVNE FCMOVNBE FCMOVNUST(0),ST(0)C1C2C9D1D9CAD2DAC3DB11ST(0),ST(3)C4CBD3DBC5CCD4DCC6CDD5DDC7CED6DE358FUCOMIFCOMIinvalidST(0),ST(0)ST(0), ST(0)E1E9F1F9reservedFUCOMIFCOMIinvalidST(0),ST(1)ST(0), ST(1)E2EAF2FAFNCLEXFUCOMIFCOMIinvalidST(0),ST(2)ST(0), ST(2)E3EBF3FBFNINITFUCOMIFCOMIinvalidST(0),ST(3)ST(0), ST(3)E4ECF4FCreservedFUCOMIFCOMIinvalidST(0),ST(4)ST(0), ST(4)E5EDF5FDinvalidFUCOMIFCOMIinvalidST(0),ST(5)ST(0), ST(5)E6EEF6FEinvalidFUCOMIFCOMIinvalidST(0),ST(6)ST(0), ST(6)ST(0), ST(6) ST(0), ST(6) ST(0), ST(6)CFD7DFFCMOVNB FCMOVNE FCMOVNBE FCMOVNUST(0),ST(7)reservedST(0), ST(5) ST(0), ST(5) ST(0), ST(5)FCMOVNB FCMOVNE FCMOVNBE FCMOVNUST(0),ST(6)F8ST(0), ST(4) ST(0), ST(4) ST(0), ST(4)FCMOVNB FCMOVNE FCMOVNBE FCMOVNUST(0),ST(5)F0ST(0), ST(3) ST(0), ST(3) ST(0), ST(3)FCMOVNB FCMOVNE FCMOVNBE FCMOVNUST(0),ST(4)E8ST(0), ST(2) ST(0), ST(2) ST(0), ST(2)FCMOVNB FCMOVNE FCMOVNBE FCMOVNUST(0), ST(7) ST(0), ST(7) ST(0), ST(7)FSTPmem80realE0ST(0), ST(1) ST(0), ST(1) ST(0), ST(1)FCMOVNB FCMOVNE FCMOVNBE FCMOVNUST(0),ST(2)mem80realST(0), ST(0) ST(0), ST(0) ST(0), ST(0)FCMOVNB FCMOVNE FCMOVNBE FCMOVNUST(0),ST(1)invalidE7EFF7FFinvalidFUCOMIFCOMIinvalidST(0),ST(7)ST(0), ST(7)Opcode and Operand Encodings24594—Rev.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
