Volume 3 General-Purpose and System Instructions (794097), страница 61
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However, two groups of instructions default to64-bit operand size and do not need a REX prefix: (1) near branches and (2) all instructions, exceptfar branches, that implicitly reference the RSP. See Table B-5 on page 400 for a list of allinstructions that default to 64-bit operand size.Zero-Extension of 32-Bit Results: Operations on 32-bit operands in 64-bit mode zero-extend thehigh 32 bits of 64-bit GPR destination registers.No Extension of 8-Bit and 16-Bit Results: Operations on 8-bit and 16-bit operands in 64-bitmode leave the high 56 or 48 bits, respectively, of 64-bit GPR destination registers unchanged.Shift and Rotate Counts: When the operand size is 64 bits, shifts and rotates use one additionalbit (6 bits total) to specify shift-count or rotate-count, allowing 64-bit shifts and rotates.Immediates: The maximum size of immediate operands is 32 bits, except that 64-bit immediatescan be MOVed into 64-bit GPRs.
Immediates that are less than 64 bits are a maximum of 32 bits,and are sign-extended to 64 bits during use.General-Purpose Instructions in 64-Bit Mode373AMD64 Technology••24594—Rev. 3.13—July 2007Displacements and Offsets: The maximum size of an address displacement or offset is 32 bits,except that 64-bit offsets can be used by specific MOV opcodes that read or write AL or rAX.Displacements and offsets that are less than 64 bits are a maximum of 32 bits, and are signextended to 64 bits during use.Undefined High 32 Bits After Mode Change: The processor does not preserve the upper 32 bitsof the 64-bit GPRs across switches from 64-bit mode to compatibility or legacy modes. Incompatibility or legacy mode, the upper 32 bits of the GPRs are undefined and not accessible tosoftware.B.2Operation and Operand Size in 64-Bit ModeTable B-1 on page 374 lists the integer instructions, showing operand size in 64-bit mode and the stateof the high 32 bits of destination registers when 32-bit operands are used.
Opcodes, such as byteoperand versions of several instructions, that do not appear in Table B-1 are covered by the generalrules described in “General Rules for 64-Bit Mode” on page 373.Table B-1. Operations and Operands in 64-Bit ModeInstruction andOpcode (hex)1AAA - ASCII Adjust after Addition37AAD - ASCII Adjust AX before DivisionD5AAM - ASCII Adjust AX after MultiplyD4AAS - ASCII Adjust AL after Subtraction3FType ofOperation2DefaultOperandSize3For 32-BitOperand Size4For 64-BitOperand Size4INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits.
If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5.
Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.374General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.For 64-BitOperand Size4ADC—Add with Carry11131581 /283 /2ADD—Signed or Unsigned Add01030581 /083 /0AND—Logical AND21232581 /483 /4ARPL - Adjust Requestor Privilege Level63BOUND - Check Array Against Bounds62BSF—Bit Scan Forward0F BCOPCODE USED as MOVSXD in 64-BIT MODEINVALID IN 64-BIT MODE (invalid-opcode exception)Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4.
Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode375AMD64 Technology24594—Rev.
3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1BSR—Bit Scan Reverse0F BDBSWAP—Byte Swap0F C8 through 0F CFType ofOperation2DefaultOperandSize3For 32-BitOperand Size4Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Promoted to64 bits.32 bitsNo GPR register results.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.For 64-BitOperand Size4Swap all 8 bytesof a 64-bit GPR.BT—Bit Test0F A30F BA /4BTC—Bit Test and Complement0F BB0F BA /7BTR—Bit Test and Reset0F B30F BA /6BTS—Bit Test and Set0F AB0F BA /5CALL—Procedure Call NearE8FF /2See “Near Branches in 64-Bit Mode” in Volume 1.Promoted to64 bits.Promoted to64 bits.64 bits64 bitsCan’t encode.6Can’t encode.6RIP = RIP + 32bit displacementsign-extended to64 bits.RIP = 64-bitoffset fromregister ormemory.Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits.
If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits.
For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.376General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1CALL—Procedure Call Far9AFF /3CBW, CWDE, CDQE—Convert Byte toWord, Convert Word to Doubleword,Convert Doubleword to QuadwordType ofOperation2DefaultOperandSize3For 32-BitOperand Size4For 64-BitOperand Size4See “Branches to 64-Bit Offsets” in Volume 1.INVALID IN 64-BIT MODE (invalid-opcode exception)Promoted to64 bits.Promoted to64 bits.98CDQ32 bitsIf selector points to a gate, thenRIP = 64-bit offset from gate, elseRIP = zero-extended 32-bit offsetfrom far pointer referenced ininstruction.CWDE: Converts32 bitsword to(size of desti- doubleword.nation regisZero-extendster)EAX to RAX.CDQE (newmnemonic):Convertsdoubleword toquadword.RAX = signextended EAX.see CWD, CDQ, CQOCDQE (new mnemonic)see CBW, CWDE, CDQECDWEsee CBW, CWDE, CDQECLC—Clear Carry FlagF8CLD—Clear Direction FlagFCCLFLUSH—Cache Line Invalidate0F AE /7CLGI—Clear Global Interrupt0F 01 DDCLI—Clear Interrupt FlagFASame aslegacy mode.Not relevant.
No GPR register results.Same asNot relevant. No GPR register results.legacy mode.Same aslegacy mode.Not relevant. No GPR register results.Same aslegacy modeNot relevant No GPR register results.Same asNot relevant. No GPR register results.legacy mode.Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2.
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