Volume 3 General-Purpose and System Instructions (794097), страница 62
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The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged.
Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode377AMD64 Technology24594—Rev. 3.13—July 2007Table B-1.
Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1CLTS—Clear Task-Switched Flag inCR00F 06CMC—Complement Carry FlagF5Type ofOperation2DefaultOperandSize3For 64-BitOperand Size4Same asNot relevant. No GPR register results.legacy mode.Same asNot relevant. No GPR register results.legacy mode.CMOVcc—Conditional Move0F 40 through 0F 4FFor 32-BitOperand Size4Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.This occurs evenif the condition isfalse.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.CMP—Compare393B3D81 /783 /7CMPS, CMPSW, CMPSD, CMPSQ—Compare StringsA7CMPXCHG—Compare and Exchange0F B1Promoted to64 bits.32 bitsCMPSD:Compare StringDoublewords.See footnote5Promoted to64 bits.32 bitsCMPSQ (newmnemonic):Compare StringQuadwordsSee footnote5Zero-extends 32bit registerresults to 64 bits.Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits.
If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged.
Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6.
The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.378General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3CMPXCHG8B—Compare andExchange Eight Bytes0F C7 /1CPUID—Processor Identification0F A2Same aslegacy mode.Same aslegacy mode.CQO (new mnemonic)Promoted to64 bits.9927DAS - Decimal Adjust AL afterSubtractionFor 64-BitOperand Size4Zero-extendsEDX and EAX to64 bits.CMPXCHG16B(new mnemonic): Compare andExchange 16Bytes.Operand sizeZero-extends 32-bit register resultsfixed at 32to 64 bits.bits.see CWD, CDQ, CQOCWD, CDQ, CQO—Convert Word toDoubleword, Convert Doubleword toQuadword, Convert Quadword to DoubleQuadwordDAA - Decimal Adjust AL after Addition32 bits.For 32-BitOperand Size4CDQ: Convertsdoubleword toquadword.32 bitsSign-extends(size of destiEAX to EDX.nation regisZero-extendster)EDX to RDX.RAX isunchanged.CQO (newmnemonic):Convertsquadword todoublequadword.Sign-extendsRAX to RDX.RAX isunchanged.INVALID IN 64-BIT MODE (invalid-opcode exception)INVALID IN 64-BIT MODE (invalid-opcode exception)2FNote:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits.
If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode379AMD64 Technology24594—Rev.
3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1DEC—Decrement by 1FF /148 through 4FType ofOperation2DefaultOperandSize3For 32-BitOperand Size4Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.OPCODE USED as REX PREFIX in 64-BIT MODEPromoted to64 bits.32 bitsRDX:RAXcontain a 64-bitZero-extends 32quotient (RAX)bit registerand 64-bitresults to 64 bits.remainder(RDX).Promoted to64 bits.64 bitsCan’t encode6DIV—Unsigned DivideF7 /6ENTER—Create Procedure StackFrameC8HLT—HaltF4Same asNot relevant. No GPR register results.legacy mode.IDIV—Signed DivideF7 /7For 64-BitOperand Size4Promoted to64 bits.32 bitsRDX:RAXcontain a 64-bitZero-extends 32quotient (RAX)bit registerand 64-bitresults to 64 bits.remainder(RDX).Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5.
Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.380General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4IMUL - Signed MultiplyRDX:RAX = RAX* reg/mem64(i.e., 128-bitresult)F7 /50F AFFor 64-BitOperand Size4Promoted to64 bits.32 bits69reg64 = reg64 *Zero-extends 32- reg/mem64bit registerresults to 64 bits. reg64 =reg/mem64 *imm32reg64 =reg/mem64 *imm86BIN—Input From PortE5Same aslegacy mode.32 bitsZero-extends 32-bit register resultsto 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.EDINC—Increment by 1FF /040 through 47OPCODE USED as REX PREFIX in 64-BIT MODEINS, INSW, INSD—Input String6DSame aslegacy mode.32 bitsPromoted to64 bits.Not relevant.INSD: Input String Doublewords.No GPR register results.See footnote5INT n—Interrupt to VectorCDINT3—Interrupt to Debug VectorSee “Long-Mode Interrupt ControlTransfers” in Volume 2.CCINTO - Interrupt to Overflow VectorCEINVALID IN 64-BIT MODE (invalid-opcode exception)Note:1.
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