Volume 3 General-Purpose and System Instructions (794097), страница 59

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3.13—July 2007AMD64 TechnologyTable A-10. x87 Opcodes and ModRM Extensions (continued)OpcodeModRMmodFieldModRM reg Field/0/1/2/3/4/5/6/7FADDFMULFCOMFCOMPFSUBFSUBRFDIVFDIVRmem64real00–BF!11mem64real mem64realDC11mem64realmem64realmem64realmem64realmem64realC0C8D0D8E0E8F0F8FADDFMULreservedreservedFSUBRFSUBFDIVRFDIVST(0),ST(0)ST(0), ST(0)ST(0), ST(0)ST(0),ST(0)ST(0), ST(0) ST(0), ST(0)C1C9D1D9E1E9F1F9FADDFMULreservedreservedFSUBRFSUBFDIVRFDIVST(1),ST(0)ST(1), ST(0)ST(1), ST(0)ST(1),ST(0)ST(1), ST(0) ST(1), ST(0)C2CAD2DAE2EAF2FAFADDFMULreservedreservedFSUBRFSUBFDIVRFDIVST(2),ST(0)ST(2), ST(0)ST(2), ST(0)ST(2),ST(0)ST(2), ST(0) ST(2), ST(0)C3CBD3DBE3EBF3FBFADDFMULreservedreservedFSUBRFSUBFDIVRFDIVST(3),ST(0)ST(3), ST(0)ST(3), ST(0)ST(3),ST(0)ST(3), ST(0) ST(3), ST(0)C4CCD4DCE4ECF4FCFADDFMULreservedreservedFSUBRFSUBFDIVRFDIVST(4),ST(0)ST(4), ST(0)ST(4), ST(0)ST(4),ST(0)C5CDD5DDE5EDF5FDFADDFMULreservedreservedFSUBRFSUBFDIVRFDIVST(5), ST(0)ST(5),ST(0)ST(5),ST(0)ST(5), ST(0)ST(4), ST(0) ST(4), ST(0)ST(5), ST(0) ST(5), ST(0)C6CED6DEE6EEF6FEFADDFMULreservedreservedFSUBRFSUBFDIVRFDIVST(6),ST(0)ST(6), ST(0)ST(6), ST(0)ST(6),ST(0)ST(6), ST(0) ST(6), ST(0)C7CFD7DFE7EFF7FFFADDFMULreservedreservedFSUBRFSUBFDIVRFDIVST(7),ST(0)ST(7), ST(0)ST(7), ST(0)ST(7),ST(0)Opcode and Operand EncodingsST(7), ST(0) ST(7), ST(0)359AMD64 Technology24594—Rev.

3.13—July 2007Table A-10. x87 Opcodes and ModRM Extensions (continued)OpcodeModRMmodFieldModRM reg Field/0/1/2/3/4/5/6/7FLDFISTTPFSTFSTPFRSTORinvalidFNSAVEFNSTSWmem64realmem64intmem64realmem64realmem98/108envmem98/108envmem16C0C8D0D8E0E8F0F8FFREEreservedFSTFSTPFUCOMFUCOMPinvalidinvalidST(0)ST(0)ST(0), ST(0)ST(0)00–BF!11ST(0)C1C9D1D9E1E9F1F9FFREEreservedFSTFSTPFUCOMFUCOMPinvalidinvalidST(1)ST(1)ST(1), ST(0)ST(1)ST(1)C2CAD2DAE2EAF2FAFFREEreservedFSTFSTPFUCOMFUCOMPinvalidinvalidST(2)ST(2)ST(2), ST(0)ST(2)D3DBE3EBF3FBFSTFSTPFUCOMFUCOMPinvalidinvalidST(3)ST(3)ST(3), ST(0)ST(3)ST(2)DD11C3CBFFREEreservedST(3)C4CCD4DCE4ECF4FCFFREEreservedFSTFSTPFUCOMFUCOMPinvalidinvalidST(4)ST(4)ST(4), ST(0)ST(4)ST(4)C5CDD5DDE5EDF5FDFFREEreservedFSTFSTPFUCOMFUCOMPinvalidinvalidST(5)ST(5)ST(5), ST(0)ST(5)D6DEE6EEF6FEinvalidinvalidST(5)C6CEFFREEreservedST(6)C7CFFFREEreservedST(7)360FSTFSTPFUCOMFUCOMPST(6)ST(6)ST(6), ST(0)ST(6)D7DFE7EFF7FFFSTFSTPFUCOMFUCOMPinvalidinvalidST(7)ST(7)ST(7), ST(0)ST(7)Opcode and Operand Encodings24594—Rev.

3.13—July 2007AMD64 TechnologyTable A-10. x87 Opcodes and ModRM Extensions (continued)OpcodeModRMmodFieldModRM reg Field/0/1/2/3/4/5/6/7FIADDFIMULFICOMFICOMPFISUBFISUBRFIDIVFIDIVRmem16intmem16intC0C8mem16intmem16intmem16intmem16intmem16intmem16intD0D8E0E8F0FADDPFMULPF8reservedinvalidFSUBRPFSUBPFDIVRPFDIVPST(0),ST(0)ST(0), ST(0)ST(0), ST(0)ST(0),ST(0)00–BF!11DE11ST(0), ST(0) ST(0), ST(0)C1C9D1D9E1E9F1F9FADDPFMULPreservedFCOMPPFSUBRPFSUBPFDIVRPFDIVPST(1),ST(0)ST(1), ST(0)ST(1), ST(0)ST(1),ST(0)ST(1), ST(0) ST(1), ST(0)C2CAD2DAE2EAF2FAFADDPFMULPreservedinvalidFSUBRPFSUBPFDIVRPFDIVPST(2),ST(0)ST(2), ST(0)ST(2), ST(0)ST(2),ST(0)ST(2), ST(0) ST(2), ST(0)C3CBD3DBE3EBF3FBFADDPFMULPreservedinvalidFSUBRPFSUBPFDIVRPFDIVPST(3),ST(0)ST(3), ST(0)ST(3), ST(0)ST(3),ST(0)ST(3), ST(0) ST(3), ST(0)C4CCD4DCE4ECF4FCFADDPFMULPreservedinvalidFSUBRPFSUBPFDIVRPFDIVPST(4),ST(0)ST(4), ST(0)ST(4), ST(0)ST(4),ST(0)C5CDD5DDE5EDF5FDFADDPFMULPreservedinvalidFSUBRPFSUBPFDIVRPFDIVPST(5), ST(0)ST(5),ST(0)ST(5),ST(0)ST(5), ST(0)ST(4), ST(0) ST(4), ST(0)ST(5), ST(0) ST(5), ST(0)C6CED6DEE6EEF6FEFADDPFMULPreservedinvalidFSUBRPFSUBPFDIVRPFDIVPST(6),ST(0)ST(6), ST(0)ST(6), ST(0)ST(6),ST(0)ST(6), ST(0) ST(6), ST(0)C7CFD7DFE7EFF7FFFADDPFMULPreservedinvalidFSUBRPFSUBPFDIVRPFDIVPST(7),ST(0)ST(7), ST(0)ST(7), ST(0)ST(7),ST(0)Opcode and Operand EncodingsST(7), ST(0) ST(7), ST(0)361AMD64 Technology24594—Rev.

3.13—July 2007Table A-10. x87 Opcodes and ModRM Extensions (continued)OpcodeModRMmodFieldModRM reg Field/0/1/2/3/4/5/6/7FILDFISTTPFISTFISTPFBLDFILDFBSTPFISTPmem16intmem16intC0C8mem16intmem16intmem80decmem64intmem80decmem64intD0D8E0E8F0reservedreservedF8reservedreservedFNSTSWFUCOMIPFCOMIPinvalidAXST(0),ST(0)ST(0), ST(0)00–BF!11C1C9D1D9E1E9F1F9reservedreservedreservedreservedinvalidFUCOMIPFCOMIPinvalidST(0),ST(1)ST(0), ST(1)C2CAD2DAE2EAF2FAreservedreservedreservedreservedinvalidFUCOMIPFCOMIPinvalidST(0),ST(2)ST(0), ST(2)C3CBD3DBE3EBF3FBreservedreservedreservedreservedinvalidFUCOMIPFCOMIPinvalidST(0),ST(3)ST(0), ST(3)DF11C4CCD4DCE4ECF4FCreservedreservedreservedreservedinvalidFUCOMIPFCOMIPinvalidST(0),ST(4)ST(0), ST(4)C5CDD5DDE5EDF5FDreservedreservedreservedreservedinvalidFUCOMIPFCOMIPinvalidST(0),ST(5)ST(0), ST(5)C6CED6DEE6EEF6FEreservedreservedreservedreservedinvalidFUCOMIPFCOMIPinvalidST(0),ST(6)ST(0), ST(6)C7CFD7DFE7EFF7FFreservedreservedreservedreservedinvalidFUCOMIPFCOMIPinvalidST(0),ST(7)ST(0), ST(7)A.2.8 rFLAGS Condition Codes for x87 OpcodesTable A-11 shows the rFLAGS condition codes specified by the opcode and ModRM bytes of theFCMOVcc instructions.362Opcode and Operand Encodings24594—Rev.

3.13—July 2007AMD64 TechnologyTable A-11. rFLAGS Condition Codes for FCMOVccOpcode(hex)ModRMmodFieldDA11DBA.3ModRMregFieldrFLAGS Valuecc MnemonicBCondition000CF = 1Below001ZF = 1EEqual010CF = 1 or ZF = 1BEBelow or Equal011PF = 1UUnordered000CF = 0NBNot Below001ZF = 0NE010CF = 0 and ZF = 0 NBENot Below or Equal011PF = 0Not UnorderedNot EqualNUOperand EncodingsRegister and memory operands are encoded using the mode-register-memory (ModRM) and the scaleindex-base (SIB) bytes that follow the opcodes.

In some instructions, the ModRM byte is followed byan SIB byte, which defines the instruction’s memory-addressing mode for the complex-addressingmodes.A.3.1 ModRM Operand ReferencesFigure A-2 on page 363 shows the format of a ModRM byte. There are three fields—mod, reg, andr/m. The reg field not only provides additional opcode bits—as described above beginning with“ModRM Extensions to One-Byte and Two-Byte Opcodes” on page 348 and ending with “x87Encodings” on page 353—but is also used with the other two fields to specify operands. The mod andr/m fields are used together with each other and, in 64-bit mode, with the REX.R and REX.B bits of theREX prefix, to specify the location of the instruction’s operands and certain of the possible addressingmodes (specifically, the non-complex modes).Bits:76mod54reg3210r/mModRMREX.R bit of REX prefix canextend this field to 4 bitsREX.B bit of REX prefix canextend this field to 4 bitsFigure A-2.Opcode and Operand Encodings513-305.epsModRM-Byte Format363AMD64 Technology24594—Rev.

3.13—July 2007The two sections below describe the ModRM operand encodings, first for 16-bit references and thenfor 32-bit and 64-bit references.16-Bit Register and Memory References. Table A-12 shows the notation and encodingconventions for register references using the ModRM reg field. This table is comparable to Table A-14on page 366 but applies only when the address-size is 16-bit. Table A-13 on page 364 shows thenotation and encoding conventions for 16-bit memory references using the ModRM byte. This table iscomparable to Table A-15 on page 367.Table A-12. ModRM Register References, 16-Bit AddressingModRM reg FieldMnemonicNotation/0/1/2/3/4/5/6/7reg8ALCLDLBLAHCHDHBHreg16AXCXDXBXSPBPSIDIreg32EAXECXEDXEBXESPEBPESIEDImmxMMX0MMX1MMX2MMX3MMX4MMX5MMX6MMX7xmmXMM0XMM1XMM2XMM3XMM4XMM5XMM6XMM7sRegESCSSSDSFSGSinvalidinvalidcRegCR0CR1CR2CR3CR4CR5CR6CR7dRegDR0DR1DR2DR3DR4DR5DR6DR7Table A-13. ModRM Memory References, 16-Bit AddressingEffective Address1ModRMmodField(binary)ModRM reg Field2/0/1/2/3/4/5/6/7ModRMr/mField(binary)Complete ModRM Byte (hex)[BX+SI]0008101820283038000[BX+DI]0109111921293139001[BP+SI]020A121A222A323A010030B131B232B333B011[SI]040C141C242C343C100[DI]050D151D252D353D101[disp16]060E161E262E363E110[BX]070F171F272F373F111[BP+DI]00Note:1.

In these combinations, “disp8” and “disp16” indicate an 8-bit or 16-bit signed displacement.2. See Table A-12 for complete specification of ModRM “reg” field.364Opcode and Operand Encodings24594—Rev. 3.13—July 2007AMD64 TechnologyTable A-13. ModRM Memory References, 16-Bit Addressing (continued)Effective Address1ModRMmodField(binary)ModRM reg Field2/0/1/2/3/4/5/6/7ModRMr/mField(binary)Complete ModRM Byte (hex)[BX+SI+disp8]4048505860687078000[BX+DI+disp8]4149515961697179001[BP+SI+disp8]424A525A626A727A010434B535B636B737B011[SI+disp8]444C545C646C747C100[DI+disp8]454D555D656D757D101[BP+disp8]464E565E666E767E110[BX+disp8]474F575F676F777F111[BX+SI+disp16]80889098A0A8B0B8000[BX+DI+disp16]81899199A1A9B1B9001[BP+SI+disp16]828A929AA2AAB2BA010838B939BA3ABB3BB011[SI+disp16]848C949CA4ACB4BC100[DI+disp16]858D959DA5ADB5BD101[BP+disp16]868E969EA6AEB6BE110[BX+disp16]878F979FA7AFB7BF111AL/AX/EAX/MMX0/XMM0C0C8D0D8E0E8F0F8000CL/CX/ECX/MMX1/XMM1C1C9D1D9E1E9F1F9001DL/DX/EDX/MMX2/XMM2C2CAD2DAE2EAF2FA010C3CBD3DBE3EBF3FB011AH/SP/ESP/MMX4/XMM4C4CCD4DCE4ECF4FC100CH/BP/EBP/MMX5/XMM5C5CDD5DDE5EDF5FD101DH/SI/ESI/MMX6/XMM6C6CED6DEE6EEF6FE110BH/DI/EDI/MMX7/XMM7C7CFD7DFE7EFF7FF111[BP+DI+disp8]01[BP+DI+disp16]10BL/BX/EBX/MMX3/XMM311Note:1.

In these combinations, “disp8” and “disp16” indicate an 8-bit or 16-bit signed displacement.2. See Table A-12 for complete specification of ModRM “reg” field.Register and Memory References for 32-Bit and 64-Bit Addressing. Ta b l e A -1 4onpage 366 shows the encoding for 32-bit and 64-bit register references using the ModRM reg field. Thefirst nine rows of Table A-14 show references when the REX.R bit is cleared to 0, and the last ninerows show references when the REX.R bit is set to 1.

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