Volume 3 General-Purpose and System Instructions (794097), страница 65
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No GPR register results.Same asNot relevant. No GPR register results.legacy mode.PREFETCHW—Prefetch L1 Data-CacheSame asLine for Writelegacy mode.0F 0D /1Not relevant. No GPR register results.PUSH—Push onto StackFF /650 through 57Promoted to64 bits.64 bitsCannot encode66A68Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results.
See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6.
The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.390General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1PUSH—Push (segment register) ontoStack0F A0 (PUSH FS)Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4Promoted to64 bits.64 bitsCannot encode6For 64-BitOperand Size40F A8 (PUSH GS)0E (PUSH CS)1E (PUSH DS)06 (PUSH ES)INVALID IN 64-BIT MODE (invalid-opcode exception)16 (PUSH SS)PUSHA, PUSHAD - Push All to GPRWords or DoublewordsINVALID IN 64-BIT MODE (invalid-opcode exception)60PUSHF, PUSHFD, PUSHFQ—PushrFLAGS Word, Doubleword, orQuadword onto StackPUSHFQ (newmnemonic):Pushes the 64-bitRFLAGSregister.Promoted to64 bits.64 bitsCannot encode6Promoted to64 bits.32 bitsZero-extends 32bit registerUses 6-bit count.results to 64 bits.Promoted to64 bits.32 bitsZero-extends 32Uses 6-bit count.bit registerresults to 64 bits.9CRCL—Rotate Through Carry LeftD1 /2D3 /2C1 /2RCR—Rotate Through Carry RightD1 /3D3 /3C1 /3RDMSR—Read Model-Specific Register0F 32Same aslegacy mode.RDX[31:0] contains MSR[63:32],RAX[31:0] contains MSR[31:0].Not relevant.Zero-extends 32-bit register resultsto 64 bits.Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits.
If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode391AMD64 Technology24594—Rev.
3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4For 64-BitOperand Size4RDPMC—Read Performance-MonitoringCountersSame aslegacy mode.0F 33RDX[31:0] contains PMC[63:32],RAX[31:0] contains PMC[31:0].Not relevant.Zero-extends 32-bit register resultsto 64 bits.RDTSC—Read Time-Stamp CounterSame aslegacy mode.RDX[31:0] contains TSC[63:32],RAX[31:0] contains TSC[31:0].Not relevant.Zero-extends 32-bit register resultsto 64 bits.Same aslegacy mode.RDX[31:0] contains TSC[63:32],RAX[31:0] contains TSC[31:0].RCX[31:0] contains the TSC_AUXNot relevant.MSR C000_0103h[31:0].
Zeroextends 32-bit register results to 64bits.0F 31RDTSCP—Read Time-Stamp Counterand Processor ID0F 01 F9REP INS—Repeat Input StringF3 6DREP LODS—Repeat Load StringF3 ADREP MOVS—Repeat Move StringF3 A5REP OUTS—Repeat Output String toPortF3 6FREP STOS—Repeat Store StringF3 ABREPx CMPS —Repeat Compare StringF3 A7Same aslegacy mode.32 bitsPromoted to64 bits.32 bitsPromoted to64 bits.32 bitsReads doubleword I/O port.See footnote5Zero-extendsEAX to 64 bits.SeeSame aslegacy mode.32 bitsPromoted to64 bits.32 bitsPromoted to64 bits.32 bitsSee footnote5footnote5No GPR register results.See footnote5Writes doubleword to I/O port.No GPR register results.See footnote5No GPR register results.See footnote5No GPR register results.See footnote5Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2.
The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged.
Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.392General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1REPx SCAS —Repeat Scan StringF3 AFRET—Return from Call NearC2C3Type ofOperation2DefaultOperandSize3Promoted to64 bits.32 bitsFor 64-BitOperand Size4No GPR register results.See footnote5See “Near Branches in 64-Bit Mode” in Volume 1.Promoted to64 bits.64 bitsNo GPR registerCannot encode.6 results.Promoted to64 bits.32 bitsSee “Control Transfers” in Volume 1and “Control-Transfer PrivilegeChecks” in Volume 2.Promoted to64 bits.32 bitsZero-extends 32bit registerUses 6-bit count.results to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerUses 6-bit count.results to 64 bits.Not relevant.See “System-Management Mode” inVolume 2.RET—Return from Call FarCBFor 32-BitOperand Size4CAROL—Rotate LeftD1 /0D3 /0C1 /0ROR—Rotate RightD1 /1D3 /1C1 /1RSM—Resume from SystemManagement Mode0F AASAHF - Store AH into Flags9ENew SMMstate-savearea.Same as legNot relevant.acy mode.No GPR register results.Promoted to64 bits.Zero-extends 32bit registerUses 6-bit count.results to 64 bits.SAL—Shift Arithmetic LeftD1 /4D3 /432 bitsC1 /4Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits.
If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6.
The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode393AMD64 Technology24594—Rev. 3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3Promoted to64 bits.32 bitsZero-extends 32bit registerUses 6-bit count.results to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.For 32-BitOperand Size4For 64-BitOperand Size4SAR—Shift Arithmetic RightD1 /7D3 /7C1 /7SBB—Subtract with Borrow191B1D81 /383 /3SCAS, SCASW, SCASD, SCASQ—Scan StringAFPromoted to64 bits.32 bitsSCASD: ScanStringDoublewords.Zero-extends 32bit registerresults to 64 bits.See footnoteSFENCE—Store Fence0F AE /7SGDT—Store Global Descriptor TableRegister0F 01 /0SCASQ (newmnemonic): ScanStringQuadwords.See footnote55Same aslegacy mode.Not relevant.
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