Volume 2 System Programming (794096), страница 74
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3.13—July 2007handler entry point must be loaded at the new memory location specified by SMBASE+8000h. Thenext time SMM is entered, the processor saves its state in the new state-save area atSMBASE+0FE00h, and begins executing the SMM handler at SMBASE+8000h. The new SMBASEaddress is used for every SMM until it is changed, or a hardware reset occurs.When SMBASE is used to relocate SMRAM to an address above 1 Mbyte, 32-bit address-sizeoverride prefixes must be used to access this memory. This is because addressing in SMM behaves as itdoes in real mode, with a 16-bit default operand size and address size.
The values in the 16-bitsegment-selector registers are left-shifted four bits to form a 20-bit segment-base address. Withoutusing address-size overrides, the maximum computable address is 10FFEFh.Because SMM memory-addressing is similar to real-mode addressing, the SMBASE address must beless than 4 Gbytes. Physical-address extensions (CR4.PAE) should not be enabled in SMM, restrictingthe SMRAM address space to the range 0h to 0FFFF_FFFFh.10.2.3 SMRAM State-Save AreaWhen an SMI occurs, the processor saves its state in the 512-byte SMRAM state-save area during thecontrol transfer into SMM.
The format of the state-save area defined by the AMD64 architecture isshown in Table 10-1. This table shows the offsets in the SMRAM state-save area relative to theSMRAM-base address. The state-save area is located between offset 0_FE00h (SMBASE+0_FE00h)and offset 0_FFFFh (SMBASE+0_FFFFh). Software should not modify offsets specified as read-onlyor reserved, otherwise unpredictable results can occur.Table 10-1.
AMD64 Architecture SMM State-Save AreaOffset (Hex)from SMBASEFE00hFE02hFE04hESContentsSizeSelectorWordAttributesWordLimitDoublewordFE08hBaseQuadwordFE10hSelectorWordAttributesWordFE12hFE14hCSLimitDoublewordFE18hBaseQuadwordFE20hSelectorWordAttributesWordFE22hFE24hFE28hSSLimitDoublewordBaseQuadwordAllowableAccessRead-OnlyRead-OnlyRead-OnlyNote:1.
The offset for the SMM-revision identifier is compatible with previous implementations.272System-Management Mode24593—Rev. 3.13—July 2007AMD64 TechnologyTable 10-1. AMD64 Architecture SMM State-Save Area (continued)Offset (Hex)from SMBASEFE30hFE32hFE34hDSContentsSizeSelectorWordAttributesWordLimitDoublewordFE38hBaseQuadwordFE40hSelectorWordAttributesWordFE42hFE44hFSLimitDoublewordFE48hBaseQuadwordFE50hSelectorWordAttributesWordFE52hFE54hGSLimitDoublewordFE58hBaseQuadwordFE60h–FE63hReservedFE64hFE66h–FE67hGDTRLimitReservedWord2 BytesBaseFE70hSelectorWordAttributesWordFE74hLDTRDoublewordFE78hBaseQuadwordFE80h–FEB3hReservedFEB6h–FEB7hIDTRLimitReservedWord2 BytesBaseFE90hSelectorWordAttributesWordFE94hTRFE98hRead-OnlyRead-OnlyRead-Only4 BytesFE88hFE92hRead-OnlyQuadwordLimitFE84hRead-Only4 BytesFE68hFE72hAllowableAccessRead-OnlyQuadwordLimitDoublewordBaseQuadwordRead-OnlyFEA0hI/O Instruction Restart RIPQuadwordRead-OnlyFEA8hI/O Instruction Restart RCXQuadwordRead-OnlyFEB0hI/O Instruction Restart RSIQuadwordRead-OnlyFEB8hI/O Instruction Restart RDIQuadwordRead-OnlyFEC0hI/O Instruction Restart DwordDoublewordRead-OnlyFEC4h–FEC7hReserved4 Bytes—Note:1.
The offset for the SMM-revision identifier is compatible with previous implementations.System-Management Mode273AMD64 Technology24593—Rev. 3.13—July 2007Table 10-1. AMD64 Architecture SMM State-Save Area (continued)Offset (Hex)from SMBASEContentsSizeFEC8hI/O Instruction RestartByteFEC9hAuto-Halt RestartByteFECAh—FECFhReservedFED0hAllowableAccessRead/Write5 Bytes—EFERQuadwordRead-OnlyFED8hSVM GuestQuadwordFEE0hSVM Guest VMCB Physical AddressQuadwordFEE8hSVM Guest Virtual InterruptQuadwordFEF0h—FEFBhReservedFEFChRead-Only10 Bytes—SMM-Revision Identifier1DoublewordRead-OnlyFF00hSMBASEDoublewordRead/WriteFF04h—FF1FhReserved27 Bytes—FF20hSVM Guest PATQuadwordFF28hSVM Host EFERQuadwordFF30hSVM Host CR4QuadwordFF38hSVM Host CR3QuadwordFF40hSVM Host CR0QuadwordFF48hCR4QuadwordFF50hCR3QuadwordFF58hCR0QuadwordFF60hDR7QuadwordFF68hDR6QuadwordFF70hRFLAGSQuadwordFF78hRIPQuadwordFF80hR15QuadwordFF88hR14QuadwordFF90hR13QuadwordFF98hR12QuadwordFFA0hR11QuadwordFFA8hR10QuadwordFFB0hR9QuadwordFFB8hR8QuadwordRead-OnlyRead-OnlyRead-OnlyRead/WriteRead/WriteNote:1.
The offset for the SMM-revision identifier is compatible with previous implementations.274System-Management Mode24593—Rev. 3.13—July 2007AMD64 TechnologyTable 10-1. AMD64 Architecture SMM State-Save Area (continued)Offset (Hex)from SMBASEContentsAllowableAccessSizeFFC0hRDIQuadwordFFC8hRSIQuadwordFFD0hRBPQuadwordFFD8hRSPQuadwordFFE0hRBXQuadwordFFE8hRDXQuadwordFFF0hRCXQuadwordFFF8hRAXQuadwordRead/WriteNote:1. The offset for the SMM-revision identifier is compatible with previous implementations.A number of other registers are not saved or restored automatically by the SMM mechanism.
See“Saving Additional Processor State” on page 281 for information on using these registers in SMM.As a reference for legacy processor implementations, the legacy SMM state-save area format is shownin Table 10-2. Implementations of the AMD64 architecture do not use this format.Table 10-2.Legacy SMM State-Save Area (Not used by AMD64Architecture)Offset (Hex)from SMBASEContentsSizeAllowableAccessFE00h—FEF7hReserved248 Bytes—FEF8hSMBASEDoublewordRead/WriteFEFChSMM-Revision IdentifierDoublewordRead-OnlyFF00hI/O Instruction RestartWordFF02hAuto-Halt RestartWordFF04h—FF87hReserved132 Bytes—FF88hGDT BaseDoublewordRead-OnlyFF8Ch—FF93hReservedQuadword—FF94hIDT BaseDoublewordRead-OnlyFF98h—FFA7hReserved16 Bytes—Read/WriteNote:1.
The offset for the SMM-revision identifier is compatible with previous implementations.System-Management Mode275AMD64 TechnologyTable 10-2.24593—Rev. 3.13—July 2007Legacy SMM State-Save Area (Not used by AMD64Architecture) (continued)Offset (Hex)from SMBASEContentsAllowableAccessSizeFFA8hESDoublewordFFAChCSDoublewordFFB0hSSDoublewordFFB4hDSDoublewordFFB8hFSDoublewordFFBChGSDoublewordFFC0hLDT BaseDoublewordFFC4hTRDoublewordFFC8hDR7DoublewordFFCChDR6DoublewordFFD0hEAXDoublewordFFD4hECXDoublewordFFD8hEDXDoublewordFFDChEBXDoublewordFFE0hESPDoublewordFFE4hEBPDoublewordFFE8hESIDoublewordFFEChEDIDoublewordFFF0hEIPDoublewordRead/WriteFFF4hEFLAGSDoublewordRead/WriteFFF8hCR3DoublewordFFFChCR0DoublewordRead-OnlyRead-OnlyRead-OnlyRead/WriteRead-OnlyNote:1.
The offset for the SMM-revision identifier is compatible with previous implementations.10.2.4 SMM-Revision IdentifierThe SMM-revision identifier specifies the SMM version and the available SMM extensionsimplemented by the processor. Software reads the SMM-revision identifier from offset FEFCh in theSMM state-save area of SMRAM.
This offset location is compatible with earlier versions of SMM.Software must not write to this location. Doing so can produce undefined results. Figure 10-3 showsthe format of the SMM-revision identifier.276System-Management Mode24593—Rev. 3.13—July 2007AMD64 TechnologyReservedDescriptionBitsSMM-Revision LevelI/O Instruction RestartSMM Base Relocation15:016173118 17 16 151 10SMM-Revision Level513-251epsFigure 10-3. SMM-Revision IdentifierThe fields within the SMM-revision identifier are:•••SMM-revision Level—Bits 15–0. Specifies the version of SMM supported by the processor. TheSMM-revision level is of the form 0_xx64h, where xx starts with 00 and is incremented for laterrevisions to the SMM mechanism.I/O Instruction Restart—Bit 16.
When set to 1, the processor supports restarting I/O instructionsthat are interrupted by an SMI. This bit is always set to 1 by implementations of the AMD64architecture. See “I/O Instruction Restart” on page 283 for information on using this feature.SMM Base Relocation—Bit 17.
When set to 1, the processor supports relocation of SMRAM. Thisbit is always set to 1 by implementations of the AMD64 architecture. See “SMBASE Register” onpage 271 for information on using this feature.All remaining bits in the SMM-revision identifier are reserved.10.2.5 SMRAM Protected AreaTwo areas are provided as safe areas for SMM code and data that are not readily accessable by nonSMM applications. The SMI handler can be located in one of these two ranges, or it can be locatedoutside of these ranges.The ASeg range is located at a fixed address from A_0000h to B_FFFFh.
The TSeg range is located ata variable base specified by the SMM_ADDR MSR with a variable size specified by the SMM_MASKMSR. These ranges must never overlap.Each CPU memory access is in the TSeg range if the following is true:Phys Addr[51:17] & SSM_MASK[51:17] = SMM_ADDR[51:17] & SSM_MASK[51:17].System-Management Mode277AMD64 Technology24593—Rev. 3.13—July 2007For example, if the TSeg range spans 256K bytes starting at address 10_0000h, then SSM_ADDR=0010_0000h and SSM_MASK=FFFC_0000h (with zeros in bits 16:0).
This results in a TSeg addressrange from 0010_0000 to 0013_FFFFh.6352 5132BASE(This is an architectural limit. A given implementation may support fewer bits.)Reserved, MBZ3117 16Reserved, MBZBASEBits63–5251–1716–0MnemonicReservedBASEReservedDescriptionReserved, Must be ZeroSMM TSeg Base AddressReserved, Must be ZeroR/WR/WFigure 10-4.•0SSM_ADDR Register FormatSMM TSeg Base Address (BASE)—Bits 51-17. Specifies the base address of the TSeg range ofprotected addresses.6352 51Reserved, MBZ32MASK(This is an architectural limit.
A given implementation may support fewer bits.)3117 16Reserved, MBZMASKBits63–5251–1716–210MnemonicReservedMASKReservedTEAEDescriptionReserved, Must be ZeroTSeg MaskReserved, Must be ZeroTseg Address Range EnableAseg Address Range Enable10TE AER/WR/WR/WR/WFigure 10-5. SSM_MASK Register Format•ASeg Address Range Enable (AE)—Bit 0. Specifies whether the ASeg address range is enabled forprotection. When the bit is set to 1, the ASeg address range is enabled for protection.
When clearedto 0, the ASeg address range is disabled for protection.278System-Management Mode24593—Rev. 3.13—July 2007••AMD64 TechnologyTSeg Address Range Enable (TE)—Bit 1. Specifies whether the TSeg address range is enabled forprotection. When the bit is set to 1, the TSeg address range is enabled for protection. When clearedto 0, the TSeg address range is disabled for protection.TSeg Mask (MASK)—Bits 51-17. Specifies the mask used to determine the TSeg range of protectedaddresses. The Phys address[51:17] is in the TSeg range if the following is true:Phys Addr[51:17] & SSM_MASK[51:17] = SMM_ADDR[51:17] & SSM_MASK[51:17].10.3Using SMM10.3.1 System-Management Interrupt (SMI)SMM is entered using the system-management interrupt (SMI).
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