Volume 2 System Programming (794096), страница 73
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If EIPV=0, the address is not guaranteed to be related to the error.Before exiting the machine-check handler, be sure to clear MCG_STATUS.MCIP to 0. MCIPindicates a machine-check exception occurred. If this bit is set when another machine-checkexception occurs, the processor enters the shutdown state.When an exception handler is able to, at a minimum, successfully log an error condition, theMCi_STATUS registers should be cleared to 0 before exiting the machine-check handler. Softwareis responsible for clearing at least the MCi_STATUS.VAL bits.Additional machine-check exception-handler portability can be added by having the handler usethe CPUID instruction to identify the processor and its capabilities.
Implementation-specificsoftware can be added to the machine-check exception handler based on the processor informationreported by CPUID.9.5.2 Reporting Correctable Machine Check ErrorsMachine-check exceptions do not occur if the error is correctable by the processor. If system softwarewishes to log and report correctable machine-check errors, a system-service routine must be providedto check the contents of the machine-check status registers for correctable errors. The service routinecan be invoked by system software on a periodic basis, or it can be manually invoked by the user asneeded.If the processor supports the machine-check registers, a service routine that reports correctable errorsshould perform the following:•Examine each status register (MCi_STATUS) in the error-reporting register banks.
For eachMCi_STATUS register with a set valid bit (VAL=1), the service routine should:- Save the contents of the MCi_STATUS register.- Save the contents of the corresponding MCi_ADDR register if MCi_STATUS.ADDRV=1.- Save the contents of the corresponding MCi_MISC register if MCi_STATUS.MISCV=1.- Check to see if MCG_STATUS.MCIP=1, which indicates that the machine-check exceptionhandler is in progress. If this is the case, then the machine-check exception handler has calledthe service routine to log the errors. In this situation, the error-logging service routine shoulddetermine whether or not the interrupted program is restartable, and report the determinationback to the exception handler. The program is not restartable if either of the following is true:- MCi_STATUS.PCC=1, which indicates the processor context is corrupted, orMachine Check Mechanism267AMD64 Technology24593—Rev. 3.13—July 2007-•••MCG_STATUS.RIPV=0, which indicates the interrupted program cannot be restarted reliablyat the instruction-pointer address pushed onto the exception-handler stack.Once the information found in the error-reporting register banks is saved, the MCi_STATUSregister should be cleared to 0.
This allows the processor to properly report any subsequent errorsin the MCi_STATUS registers.The service routine can save the time-stamp counter with each error logged. This can help indetermining how frequently errors occur. For further information, see “Time-Stamp Counter” onpage 344.In multiprocessor configurations, the service routine can save the processor-node identifier. Thiscan help locate a failing multiprocessor-system component, which can then be isolated from therest of the system. For further information, see the documentation for particular implementationsof the architecture.268Machine Check Mechanism24593—Rev.
3.13—July 200710AMD64 TechnologySystem-Management ModeSystem-management mode (SMM) is an operating mode designed for system-control activities likepower management. Normally, these activities are transparent to conventional operating systems andapplications. SMM is used by system-specific BIOS (basic input-output system) and specialized lowlevel device drivers, rather than the operating system.The SMM interrupt-handling mechanism differs substantially from the standard interrupt-handlingmechanism described in Chapter 8, “Exceptions and Interrupts.” SMM is entered using a specialexternal interrupt called the system-management interrupt (SMI).
After an SMI is received by theprocessor, the processor saves the processor state in a separate address space, called SMRAM. TheSMM-handler software and data structures are also located in the SMRAM space. Interrupts andexceptions that ordinarily cause control transfers to the operating system are disabled when SMM isentered. The processor exits SMM, restores the saved processor state, and resumes normal executionby using a special instruction, RSM.In SMM, address translation is disabled and addressing is similar to real mode. SMM programs canaddress up to 4 Gbytes of physical memory.
See “SMM Operating-Environment” on page 279 foradditional information on memory addressing in SMM.The following sections describe the components of the SMM mechanism:••“SMM Resources” on page 270—this section describes SMRAM, the SMRAM save-state areaused to hold the processor state, and special SMRAM save-state entries used in support of SMM.“Using SMM” on page 279—this section describes the mechanism of entering and exiting SMM.It also describes SMM memory allocation, addressing, and interrupts and exceptions.Of these mechanisms, only the format of the SMRAM save-state area differs between the AMD64architecture and the legacy architecture.10.1SMM DifferencesThere are functional differences between the SMM support in the AMD64 architecture and the SMMsupport found in previous architectures.
These are:•••••The SMRAM state-save area layout is changed to hold the 64-bit processor state.The initial processor state upon entering SMM is expanded to reflect the 64-bit nature of theprocessor.New conditions exist that can cause a processor shutdown while in SMM.The auto-halt restart and I/O-instruction restart entries in the SMRAM state-save area are one byteeach instead of two bytes each.SMRAM caching considerations are modified because the legacy FLUSH# external signal(writeback, if modified, and invalidate) is not supported on implementations of the AMD64architecture.System-Management Mode269AMD64 Technology•24593—Rev.
3.13—July 2007Some previous AMD x86 processors saved and restored the CR2 register in the SMRAM statesave area. This register is not saved by the SMM implementation in the AMD64 architecture.SMM handlers that save and restore CR2 must perform the operation in software.10.2SMM ResourcesThe SMM resources supported by the processor consist of SMRAM, the SMRAM state-save area, andspecial entries within the SMRAM state-save area. In addition to the save-state area, SMRAMincludes space for the SMM handler.10.2.1 SMRAMSMRAM is the memory-address space accessed by the processor when in SMM. The default size ofSMRAM is 64 Kbytes and can range in size between 32 Kbytes and 4 Gbytes.
System logic can usephysically separate SMRAM and main memory, directing memory transactions to SMRAM afterrecognizing SMM is entered, and redirecting memory transactions back to system memory afterrecognizing SMM is exited. When separate SMRAM and main memory are used, the system designerneeds to provide a method of mapping SMRAM into main memory so that the SMI handler and datastructures can be loaded.Figure 10-1 on page 271 shows the default SMRAM memory map.
The default SMRAM codesegment (CS) has a base address of 0003_0000h (the base address is automatically scaled by theprocessor using the CS-selector register, which is set to the value 3000h). This default SMRAM-baseaddress is known as SMBASE. A 64-Kbyte memory region, addressed from 0003_0000h to0003_FFFFh, makes up the default SMRAM memory space. The top 32 Kbytes (0003_8000h to0003_FFFFh) must be supported by system logic, with physical memory covering that entire addressrange. The top 512 bytes (0003_FE00h to 0003_FFFFh) of this address range are the default SMMstate-save area.
The default entry point for the SMM interrupt handler is located at 0003_8000h.270System-Management Mode24593—Rev. 3.13—July 2007AMD64 TechnologySMRAMSMM State-Save Area0003_FFFFh(SMBASE+FFFFh)0003_FE00hSMM Handler0003_8000h(SMBASE+8000h)0003_0000h(SMBASE)513-250.epsFigure 10-1. Default SMRAM Memory Map10.2.2 SMBASE RegisterThe format of the SMBASE register is shown in Figure 10-2. SMBASE is an internal processorregister that holds the value of the SMRAM-base address.
SMBASE is set to 30000h after a processorreset.310SMRAM BaseFigure 10-2.SMBASE RegisterIn some operating environments, relocation of SMRAM to a higher memory area can provide morelow memory for legacy software. SMBASE relocation is supported when the SMM-base relocation bitin the SMM-revision identifier (bit 17) is set to 1. In processors implementing the AMD64architecture, SMBASE relocation is always supported.Software can only modify SMBASE (relocate the SMRAM-base address) by entering SMM,modifying the SMBASE image stored in the SMRAM state-save area, and exiting SMM. The SMM-System-Management Mode271AMD64 Technology24593—Rev.
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