Volume 2 System Programming (794096), страница 69

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If IOPL<3,the INTn causes a #GP exception.When cleared to 0, the INTn instruction is directed through the IVT for the virtual-8086 programto the corresponding virtual-8086 interrupt handler.Only software interrupts can be redirected using the IRB mechanism. External interrupts areasynchronous events that occur outside the context of a virtual-8086 program. Therefore, externalinterrupts require system-software intervention to determine the appropriate context for the interrupt.The VME extensions described in “VIF and VIP Extensions for External Interrupts” on page 247 areprovided to assist system software with external-interrupt intervention.248Exceptions and Interrupts24593—Rev. 3.13—July 2007AMD64 Technology8.10.2 Protected Mode Virtual InterruptsThe protected-mode virtual-interrupt (PVI) bit in CR4 enables support for interrupt virtualization inprotected mode.

When enabled, the processor maintains program-specific VIF and VIP bits similar tothe manner defined by the virtual-8086 mode extensions (VME). However, unlike VME, only the STIand CLI instructions are affected by the PVI extension. When a program is running at CPL=3, it canuse STI and CLI to set and clear its copy of the VIF flag without causing a general-protectionexception. The last section of Table 8-11 on page 250 describes the behavior of instructions thatmodify the IF bit when PVI extensions are enabled.The interrupt redirection bitmap (IRB) defined by the VME extensions is not supported by the PVIextensions.8.10.3 Effect of Instructions that Modify EFLAGS.IFTable 8-11 on page 250 shows how the behavior of instructions that modify the IF bit are affected bythe VME and PVI extensions.

The table columns specify the following:•••••••Operating Mode—the processor mode in effect when the instruction is executed.Instruction—the IF-modifying instruction.IOPL—the value of the EFLAGS.IOPL field.VIP—the value of the EFLAGS.VIP bit.#GP—indicates whether the conditions in the first four columns cause a general-protectionexception (#GP) to occur.Effect on IF Bit—indicates the effect the conditions in the first four columns have on theEFLAGS.IF bit and the image of EFLAGS.IF on the stack.Effect on VIF Bit—indicates the effect the conditions in the first four columns have on theEFLAGS.VIF bit and the image of EFLAGS.VIF on the stack.Exceptions and Interrupts249AMD64 TechnologyTable 8-11.24593—Rev.

3.13—July 2007Effect of Instructions that Modify the IF BitOperating Mode Instruction IOPL VIP #GPReal ModeCR0.PE=0EFLAGS.VM=0CR4.VME=0CR4.PVI=0CLIIF = 0STIIF = 1PUSHFEFLAGS.IF Stack Image = IFIF = 0IRETIF = EFLAGS.IF Stack ImageProtected ModePUSHFPOPF≥CPLnoIF = 0<CPLyes—≥CPLnoIF = 1<CPLyes—xEFLAGS.IF Stack Image = IF≥CPLIF = EFLAGS.IF Stack Image<CPLIRETNo ChangenoINTn gateCLISTICR0.PE=1EFLAGS.VM=1CR4.VME=0CR4.PVI=xPUSHFPOPFINTn gateIRETIRETDEFLAGS.IF Stack Image = IFIF = 0xIF = EFLAGS.IF Stack ImageIRETDVirtual-8086ModeIF = EFLAGS.IF stack imageINTnSTIEffect on VIF BitEFLAGS.IF Stack Image = IFnoPOPFCLICR0.PE=1EFLAGS.VM=0CR4.VME=xCR4.PVI=0Effect on IF Bit3noIF = 0<3yes—3noIF = 1<3yes—3noEFLAGS.IF Stack Image = IF<3yes—3noIF = EFLAGS.IF Stack Image<3yes—3noEFLAGS.IF Stack Image = IFIF = 0<3yes—3noIF = EFLAGS.IF Stack Image<3yes—3noIF = EFLAGS.IF Stack Image<3yes—Note:Gray-shaded boxes indicate the bits are unsupported (ignored) in the specified operating mode.“x” indicates the value of the bit is a “don’t care”.“—” indicates the instruction causes a general-protection exception (#GP).Note:1.

If the EFLAGS.IF stack image is 0, no #GP exception occurs and the IRET instruction is executed.2. If the EFLAGS.IF stack image is 1, the IRET is not executed, and a #GP exception occurs.250Exceptions and Interrupts24593—Rev. 3.13—July 2007Table 8-11.AMD64 TechnologyEffect of Instructions that Modify the IF Bit (continued)Operating Mode Instruction IOPL VIP #GPCLI3<33STIPUSHFPUSHFDVirtual-8086Modewith VMEExtensionsCR0.PE=1EFLAGS.VM=1CR4.VME=1CR4.PVI=x<33<33<33POPFPOPFD<33<3xnoIRETD<33<3No ChangeNo ChangeVIF = 0noIF = 1No ChangenoNo ChangeVIF = 11yes—xnoEFLAGS.IF Stack Image = IFNot PushedNot PushedEFLAGS.IF Stack Image = VIFnoEFLAGS.IF Stack Image = IFEFLAGS.VIF Stack Image = VIFyes—xnoIF = EFLAGS.IF Stack ImageNo Change0noNo ChangeVIF = EFLAGS.IF Stack Image1yes—noIF = EFLAGS.IF Stack Imageyes—xxno<3IRETIF = 0xx3Effect on VIF Bit03INTn gateEffect on IF BitNo ChangeEFLAGS.IF Stack Image = IFIF = 0No ChangeNo ChangeEFLAGS.IF Stack Image = VIFVIF = 0xnoIF = EFLAGS.IF Stack ImageNo Change0noNo ChangeVIF = EFLAGS.IF Stack ImageNo ChangeVIF = EFLAGS.IF Stack Image11xnoyes2 —noIF = EFLAGS.IF Stack Imageyes—VIF = EFLAGS.IF Stack ImageNote:Gray-shaded boxes indicate the bits are unsupported (ignored) in the specified operating mode.“x” indicates the value of the bit is a “don’t care”.“—” indicates the instruction causes a general-protection exception (#GP).Note:1.

If the EFLAGS.IF stack image is 0, no #GP exception occurs and the IRET instruction is executed.2. If the EFLAGS.IF stack image is 1, the IRET is not executed, and a #GP exception occurs.Exceptions and Interrupts251AMD64 TechnologyTable 8-11.24593—Rev. 3.13—July 2007Effect of Instructions that Modify the IF Bit (continued)Operating Mode Instruction IOPL VIP #GPCLI3<33Protected Modewith PVIExtensionsCR0.PE=1EFLAGS.VM=0CR4.VME=xCR4.PVI=1CPL=3STI<3xnoIRETNo ChangeVIF = 0noIF = 1No ChangenoNo ChangeVIF = 11yes—POPFIRETDNo ChangexPUSHFDINTn gateIF = 0EFLAGS.IF Stack Image = IFIF = EFLAGS.IF Stack ImagexEffect on VIF Bit0PUSHFPOPFDEffect on IF BitxnoEFLAGS.IF Stack Image = IFIF = 0 (if interrupt gate)IF = EFLAGS.IF Stack ImageNot PushedEFLAGS.VIF Stack Image = VIFNo ChangeVIF = 0No ChangeNo ChangeVIF = EFLAGS.VIF Stack ImageNote:Gray-shaded boxes indicate the bits are unsupported (ignored) in the specified operating mode.“x” indicates the value of the bit is a “don’t care”.“—” indicates the instruction causes a general-protection exception (#GP).Note:1.

If the EFLAGS.IF stack image is 0, no #GP exception occurs and the IRET instruction is executed.2. If the EFLAGS.IF stack image is 1, the IRET is not executed, and a #GP exception occurs.252Exceptions and Interrupts24593—Rev. 3.13—July 20079AMD64 TechnologyMachine Check MechanismThe machine-check mechanism allows the processor to detect and report a variety of hardware errors.The types of errors that can be reported include:••••Cache errors associated with reading and writing data, probing, cache-line fills, and cache-linewritebacks.Parity errors associated with the caches and TLBs.ECC errors associated with the caches and DRAM.Bus errors associated with reading and writing on the processor external bus.Software can enable the processor to report machine-check errors through the machine-checkexception (for additional information, see “#MC—Machine-Check Exception (Vector 18)” onpage 220).

Most machine-check error conditions do not allow reliable restarting of interruptedprograms. System software instead uses the machine-check mechanism to report the source ofhardware problems for possible servicing.The basic machine-check mechanism is consistent across processor implementations, but the errorreporting registers are model specific. Processor implementations are not required to support themechanism, and those implementations that do support it can vary in how the mechanism works.9.1Determining Machine-Check SupportThe availability of machine-check registers and support of the machine-check exception isimplementation dependent. System software executes the CPUID instruction to determine whether aprocessor implements these features. After CPUID is executed, the values of the machine-checkarchitecture (MCA) bit and the machine-check exception (MCE) bit loaded in the EDX registerindicate whether the processor implements the machine-check registers and the machine-checkexception, respectively.

See “Processor Feature Identification” on page 61 for more information onusing the CPUID instruction to determine the level of machine-check support.Once system software determines that the machine-check registers are available, it must determine theextent of processor support for the machine-check mechanism. This is accomplished by reading themachine-check capabilities register (MCG_CAP). See “Machine-Check Global-Capabilities Register”on page 255 for more information on interpreting the MCG_CAP contents.Implementation-specific information concerning the machine-check mechanism can be found in theBIOS writer’s guide for the implementation.9.2Machine-Check ErrorsThe following classes of machine-check errors are defined for the AMD64 architecture:Machine Check Mechanism253AMD64 Technology••24593—Rev.

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