Volume 2 System Programming (794096), страница 70
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3.13—July 2007Recoverable—The error has been corrected by the processor. Recoverable errors do not cause amachine check exception (#MC). However, the error is still logged in the machine-check registers.It is the responsibility of system software to periodically poll the machine-check registers todetermine whether recoverable errors have occurred.Fatal/Unrecoverable—The error cannot be corrected by the processor. Unrecoverable errors causea machine check exception if CR4.MCE is set to 1.In both cases, the contents of the machine-check registers are maintained through a warm reset, whichallows errors to be reported even if a reset occurs.9.2.1 Error SourcesImplementations can detect errors from any number of sources located within the various processorunits.
Those processor units can include the following:•••••Data-Cache Unit (DC)—Includes the cache structures that hold data and tags, the data TLBs, andcache-probing logic.Instruction-Cache Unit (IC)—Includes the cache structures that hold instructions and tags, theinstruction TLBs, and cache-probing logic.Bus Unit (BU)—Includes the L2 cache and any external caches.Load/Store Unit (LS)—Includes logic used to manage loads and stores.Northbridge (NB)—Includes the system-bus interface and DRAM controller.A given processor implementation can monitor machine-check errors in sources other than those listedabove.
The number is implementation-specific and is determined by examining the MCG_CAPregister (see “Machine-Check Global-Capabilities Register” on page 255). For further information,see the documentation for particular implementations of the architecture.9.3Machine Check MSRsThe AMD64 architecture defines a set of model-specific registers (MSRs) in support of the machinecheck mechanism. These registers include:••Global-status and global-control registers:- Machine-check global-capabilities register (MCG_CAP).- Machine-check global-status register (MCG_STATUS).- Machine-check global-control register (MCG_CTL).- CPU watchdog timer register (CPU_WATCHDOG_TIMER)Error-reporting register banks, each containing:- Machine-check control register (MCi_CTL).- Machine-check status register (MCi_STATUS).- Machine-check address register (MCi_ADDR).254Machine Check Mechanism24593—Rev.
3.13—July 2007AMD64 Technology- Machine-check miscellaneous error-information register (MCi_MISCj).Each error-reporting register bank is associated with a specific processor unit (or group ofprocessor units).•CPU Watchdog Timer register (CPU_WATCHDOG_TIMER)In some cases, the machine-check handler cannot be invoked due to an error, the error-reportingregisters retain their values through a warm reset. (A warm reset is a reset that occurs while theprocessor is powered up, as opposed to a cold reset, which occurs during power-up.) This allows theBIOS or other system-boot software to recover and report information associated with the error.The RDMSR and WRMSR instructions are used to read and write the machine-check MSRs.
See“Machine-Check MSRs” on page 459 for a listing of the machine-check MSR numbers and their resetvalues. The following sections describe each machine-check MSR and its function.9.3.1 Global Status and Control RegistersThe global-status and global-control MSRs supported by the machine-check mechanism include theMCG_CAP, MCG_STATUS, and MCG_CTL registers.Machine-Check Global-Capabilities Register.
Figure 9-1 shows the format of the machine-checkglobal-capabilities register (MCG_CAP). MCG_CAP is a read-only register that specifies themachine-check mechanism capabilities supported by the processor implementation.6332Reserved3110 9CWTPReservedBits63–10987-0MnemonicReservedCWTPCTLPCountDescriptionR/WCPU Watchdog Timer PresentMCG_CTL_PMCG_CTL register presentNumber of reporting banksRRRFigure 9-1.8CTLP70CountMCG_CAP RegisterThe fields within the MCG_CAP register are:•Count—Bits 7–0. This field specifies how many error-reporting register banks are supported by theprocessor implementation.Machine Check Mechanism255AMD64 Technology••24593—Rev.
3.13—July 2007MCG_CTL_PMCG_CTL Register Present (CTLP)—Bit 8. This bit specifies whether or not theMCG_CTL_PMCG_CTL register is supported by the processor. When the bit is set to 1, theregister is supported. When the bit is cleared to 0, the register is unsupported.CPU Watchdog Timer Present (CWTP)—Bit 9. This bit specifies whether the CPU watchdog timeris supported by the CPU core. When this bit is set to 1, the CPU watchdog timer is supported.When cleared to 0, the CPU watchdog timer is not supported.All remaining bits in the MCG_CAP register are reserved.
Writing values to the MCG_CAP registerproduces undefined results.Machine-Check Global-Status Register. Figure 9-2 shows the format of the machine-check global-status register (MCG_STATUS). MCG_STATUS provides basic information about the processor stateafter the occurrence of a machine-check error.6332Reserved313ReservedBits63–3210MnemonicReservedMCIPEIPVRIPVDescriptionR/WMachine Check In-ProgressError IP Valid FlagRestart IP Valid FlagR/WR/WR/W2MCIP1 0E RI IP PV VFigure 9-2. MCG_STATUS RegisterThe fields within the MCG_STATUS register are:•••Restart-IP Valid (RIPV)—Bit 0. When this bit is set to 1, the interrupted program can be reliablyrestarted at the instruction addressed by the instruction pointer pushed onto the stack by themachine-check error mechanism.
If this bit is cleared to 0, the interrupted program cannot bereliably restarted.Error-IP Valid (EIPV)—Bit 1. When this bit is set to 1, the instruction that is referenced by theinstruction pointer pushed onto the stack by the machine-check error mechanism is responsible forthe machine-check error. If this bit is cleared to 0, it is possible that the instruction referenced bythe instruction pointer is not responsible for the machine-check error.Machine Check In-Progress (MCIP)—Bit 2. When this bit is set to 1, it indicates that a machinecheck error is in progress. If another machine-check error occurs while this bit is set, the processor256Machine Check Mechanism24593—Rev.
3.13—July 2007AMD64 Technologyenters the shutdown state. The processor sets this bit whenever a machine check exception isgenerated. Software is responsible for clearing it after the machine check exception is handled.All remaining bits in the MCG_STATUS register are reserved.Machine-Check Global-Control Register. Figure 9-3 on page 257 shows the format of themachine-check global-control register (MCG_CTL). MCG_CTL is used by software to controlreporting machine-check errors from various sources.
Each error-reporting register bank supported bythe processor is controlled by a corresponding enable bit in this register. Setting all bits to 1 in thisregister enables all error-reporting register banks. The number of controls and how they are used isimplementation-specific (for further information, see the documentation for particularimplementations of the architecture). The presence of the MCG_CTL register is indicated by theMCG_CAP register MCG_CTL_P bit, described on page 255.63EN…6320E E E… N N N2 1 0Error-Reporting Register-Bank Enable BitsFigure 9-3.1MCG_CTL RegisterCPU Watchdog Timer Register. The CPU watchdog timer is used to generate a machine checkcondition when an instruction does not complete within a time period specified by the CPU WatchdogTimer register.
The timer restarts the count each time an instruction completes, when enabled by theCPU Watchdog Timer Enable bit. The time period is determined by the Count Select and Time Basefields. The timer does not count during halt or stop-grant. The machine check condition is controlledby the appropriate MCi_CTL register.The format of the CPU watchdog timer is shown in Figure 9-4.6332Reserved, MBZ3176Reserved, MBZBits63–76–32–10MnemonicReservedCSTBENDescriptionReserved, Must be ZeroCPU Watchdog Timer Count SelectCPU Watchdog Timer Time BaseCPU Watchdog Timer Enable3CS21TB0ENR/WR/WR/WR/WFigure 9-4.
CPU Watchdog Timer Register FormatMachine Check Mechanism257AMD64 Technology24593—Rev. 3.13—July 2007CPU Watchdog Timer Enable (EN) - Bit 0. This bit specifies whether the CPU Watchdog Timer isenabled. When the bit is set to 1, the timer increments and generates a machine check when the timerexpires. When cleared to 0, the timer does not increment and no machine check is generated.CPU Watchdog Timer Time Base (TB) - Bits 2-1. Specifies the time base for the time-out periodindicated in the Count Select field. The allowable time base values are provided in Table 9-1..Table 9-1.CPU Watchdog Timer Time BaseBitsTime Base00b1 millisecond01b1 microsecond10b5 nanoseconds11bReservedCPU Watchdog Timer Count Select (CS) - Bits 6-3.
Specifies the time period required for the CPUWatchdog Timer to expire. The time period is this value times the time base specified in the Time Basefield. The allowable values are shown in Table 9-2.Table 9-2.CPU Watchdog Timer Count SelectBitsValue0000b40950001b20470010b10230011b5110100b2550101b1270110b630111b311000b81911001b163831010b1111bReserved9.3.2 Error-Reporting Register BanksError-reporting register banks contain the following registers:••••Machine-check control registers (MCi_CTL).Machine-check status register (MCi_STATUS).Machine-check address register (MCi_ADDR).Machine-check miscellaneous error-information register (MCi_MISCj).258Machine Check Mechanism24593—Rev.
3.13—July 2007AMD64 TechnologyThe i in each register name corresponds to the number of a supported register bank. Each errorreporting register bank is associated with a specific processor unit (or group of processor units). Thenumber of error-reporting register banks is implementation-specific. For more information, see theBIOS and Kernel Developer’s Guide for AMD Athlon™ 64 and AMD Opteron™ Processors (order#26094) for particular implementations of the AMD64 architecture.Software reads the MCG_CAP register to determine the number of supported register banks.
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