Volume 2 System Programming (794096), страница 71
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The firsterror-reporting register (MC0_CTL) always starts with MSR address 400h, followed byMC0_STATUS (401h), MC0_ADDR (402h), and MC0_MISC (403h). Error-reporting-register MSRaddresses are assigned sequentially through the remaining supported register banks. Using thisinformation, software can access all error-reporting registers in an implementation-independentmanner.Machine-Check Control Registers. The machine-check control registers (MCi_CTL), as shown inFigure 9-5 on page 259, contain an enable bit for each error source within an error-reporting registerbank.
Setting an enable bit to 1 enables error-reporting for the specific feature controlled by the bit, andclearing the bit to 0 disables error reporting for the feature. For more information, see the BIOS andKernel Developer’s Guide for the AMD Athlon™ 64 and AMD Opteron™ Processors (order# 26094)for particular implementations of the AMD64 architecture.63EN…632Error-Reporting Register-Bank Enable BitsFigure 9-5.10E E E… N N N2 1 0MCi_CTL RegistersMachine-Check Status Registers.
Each error-reporting register bank includes a machine-checkstatus register (MCi_STATUS) that the processor uses to report machine-check error information. Themachine-check mechanism writes the status-register bits when an error is detected, and sets the validbit in the register (bit 63) to 1, indicating that the status information is valid. Error reporting for thedetected error does not need to be enabled for the processor to write the status register. Error reportingmust be enabled for the error to result in a machine-check exception. Software is responsible forclearing the status register after the exception has been handled.
Attempting to write a value other than0 to an MCi_STATUS register will raise a general protection (#GP) exception.Figure 9-6 shows the format of the MCi_STATUS register.Machine Check Mechanism259AMD64 Technology63 62 61 60 59MOVIV U EASE C NLCRV58ADDRV24593—Rev. 3.13—July 200757 5632PCCOther Information3116 150Model-Specific Error CodeBits Mnemonic Description63VALValid62OVERStatus Register Overflow61UCUncorrected Error60ENError Condition Enabled59MISCVMiscellaneous-Error Register Valid58ADDRVError-Address Register Valid57PCCProcessor-Context Corrupt56–32Other Information31–16Model-Specific Error Code15–0MCA Error Code*Applications can only clear this bit to 0.MCA Error CodeR/WR/W*R/W*R/W*R/W*R/W*R/W*R/W*R/W*R/W*R/W*Figure 9-6.
MCi_STATUS Register9.3.3 Error CodesWhen a machine-check error occurs, the processor loads an error code into the appropriateMCi_STATUS register MCA error-code field. The MCi_STATUS.VAL bit is set to 1, indicating thatthe MCi_STATUS register contents are valid. The machine-check mechanism also allows theprocessor to load a model-specific error code into the MCi_STATUS register.MCA error-codes are used to report errors in the memory hierarchy, the system bus, and the systeminterconnection logic. Error-codes are divided into subfields that are used to describe the cause of anerror. The information is implementation specific.
It includes the location in the memory hierarchywhere the error occurred and the type of transaction that caused the error. For further information, seethe documentation for particular implementations of the architecture.The fields within the MCi_STATUS register are:•MCA Error Code—Bits 15–0.
This field encodes information about the error, including:- The type of transaction that caused the error.- The memory-hierarchy level involved in the error.- The type of request that caused the error.- Other information concerning the transaction type.260Machine Check Mechanism24593—Rev.
3.13—July 2007••••••••AMD64 TechnologySee the appropriate implementation specific BIOS and kernel developer’s guide for information onthe format and encoding of the MCA error code.Model-Specific Error Code—Bits 31–16. This field encodes model-specific information about theerror. For further information, see the documentation for particular implementations of thearchitecture.Other Information—Bits 56–32. This field holds model-specific error information. Softwareshould not rely on the field definitions being consistent between processor implementations.Presently, the bits in this field are defined as:- Bits 44–32—Reserved.- Bit 45—When set to 1, this bit indicates the error is an uncorrectable ECC error.- Bit 46—When set to 1, this bit indicates the error is a correctable ECC error.- Bits 54–47—This field holds the ECC syndrome when an ECC error occurs.- Bits 56–55—Reserved.PCC—Bit 57.
When set to 1, this bit indicates that the processor state is likely to be corrupt due tothe machine-check error. In this case, it is possible software cannot restart the processor reliably.When this bit is cleared to 0, the processor state is not corrupted by the machine-check error. If thePCC bit is set in any error bank, the processor will clear RIPV and EIPV in the MCG_Statusregister.ADDRV—Bit 58.
When set to 1, this bit indicates that the address saved in the corresponding errorreporting address register (MCi_ADDR) is valid, and contains the address where the error wasdetected. When this bit is cleared to 0, MCi_ADDR does not contain a valid error address.MISCV—Bit 59. When set to 1, this bit indicates that additional information about the machinecheck error is saved in the corresponding error-reporting miscellaneous register (MCi_MISC).This bit is cleared to 0 when the MCi_MISC registers are not implemented.EN—Bit 60.
When set to 1, this bit indicates that the error condition is enabled in thecorresponding error-reporting control register (MCi_CTL). Errors disabled by MCi_CTL do notcause a machine-check exception, but the machine-check mechanism can log errors when errorreporting is disabled in MCi_CTL.UC—Bit 61. When set to 1, this bit indicates that the processor did not correct the error condition.When this bit is cleared to 0, the processor corrected the error condition.OVER—Bit 62. This bit is set to 1 by the processor if the VAL bit is already set to 1 as theprocessor attempts to load error information into MCi_STATUS.
This indicates that the results of aprevious machine-check error are still in the MCi_STATUS register. In this situation, the machinecheck mechanism handles the contents of MCi_STATUS as follows:- Status for an enabled error replaces status for a disabled error.- Status for an uncorrectable error replaces status for a correctable error.- Status for an enabled uncorrectable error is never replaced.Machine Check Mechanism261AMD64 Technology•24593—Rev. 3.13—July 2007VAL—Bit 63.
This bit is set to 1 by the processor if the contents of MCi_STATUS are valid.Software should clear the VAL bit after reading the MCi_STATUS register, otherwise a subsequentmachine-check error sets the OVER bit as described above.Machine-Check Address Registers.
Each error-reporting register bank includes a machine-checkaddress register (MCi_ADDR) that the processor uses to report the address associated with themachine-check error. The address field can hold either a virtual (linear) or physical address, dependingon the type of error. For further information, see the documentation for particular implementations ofthe architecture.
The contents of this register are valid only if the ADDRV bit in the correspondingMCi_STATUS register is set to 1.Machine-Check Miscellaneous-Error Information Registers (MCi_MISCj). Each error-reportingregister bank can include a machine-check miscellaneous (thresholding) register that the processoruses to report additional error information associated with error thresholding:Error thresholding is a mechanism provided by hardware to:••count machine check correctable errors(optionally) generate an APIC-based interrupt when a programmed number of correctable errorshas been counted. Software can program the error count required to cause the interrupt.Processor hardware counts correctable errors and ensures that multiple correctable error sources do notshare the same thresholding register. Software can use this information to predict which componentsmight soon fail due to uncorrectable errors and schedule their replacement.
Whether other errors(uncorrectable or deferred) are also counted is implementation dependent.Threshold counters increment for machine-check correctable errors that are conditioned to be“logged”. To enable error logging:••machine checks must be globally enabled for the bank, andother implementation-specific mechanisms that allow logging of machine checks for the bankmust be enabled.
Logging is different from reporting, so reporting does not have to be enabled(MCi_CTL[ErrorReportingEnable] = 0) to increment the threshold counters.There are two types of machine check miscellaneous error-information (thresholding) registers:••MCi_MISC0—the first thresholding register in the bank. It has the following characteristics:- valid only if the MISCV bit in the corresponding MCi_STATUS register is set to 1.- located at the MSR address of the associated MCi_CTL +3.- indicates the existence of additional thresholding registers for the bank whenMCi_MISC0[BlkPtr] > 0.MCi_MISCj (j > 0)—Additional thresholding registers in the bank, with the followingcharacteristics:- up to 8 additional MCi_MISCj registers can be supported per bank- thresholding registers reside in contiguous error MSR blocks, with MCi_MISC1 addressed by:262Machine Check Mechanism24593—Rev.
3.13—July 2007AMD64 TechnologyMCi_MISC1 address = C000_0400h + (MCi_MISC0[BlkPtr] << 3)(See Figure 9-7 below.)MCi_CTLMCi_STATUSMCi_ADDRMCi_MISC0MCi_MISC1C000_0400h + (MCi_MISC0[BlkPtr] << 3)MCi_MISC2MCi_MISC3MCi_MISC4....Figure 9-7.63 62CVTARLP61 60LKD56 55Reserved31MCi_MISC1 Addressing52 51 50 49 48 47CINNOLVTOFFTTFET32ERRCT24 230ReservedBLKPBits63626160–5655–525150–494847–3231–2423–0MnemonicVALCTRPLKDReservedLVTOFFCNTEINTTOFERRCTBLKPReservedDescriptionValidCounter PresentLockedR/WRRR/WReset1b1b0bLVT OffsetCounter EnableInterrupt TypeOverflowError CounterBlock pointer for additional MISC registersR/WR/WR/WR/WR/WR0000b0b00bXbXXXXhFigure 9-8. Machine Check Miscellaneous Error-Information Register (MCi_MISCj)Machine Check Mechanism263AMD64 Technology24593—Rev.
3.13—July 2007The fields within the MCi_MISCj register are:•••••••••Valid (VAL)—Bit 63. When set to 1, indicates that the counter present (CTRP) and block pointer(BLKP) fields in this register are valid.Counter Present (CTRP)—Bit 62. When set to 1, indicates the presence of a threshold counter.Locked (LKD)—Bit 61. When set to 1, indicates that the threshold counter is not available for OSuse.
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